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examples/de1: use of MigIo

This commit is contained in:
Florent Kermarrec 2012-09-12 22:20:07 +02:00
parent fc6225273b
commit c7e2b0c43e
2 changed files with 14 additions and 12 deletions
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5
examples/de1/constraints.py
View File

@ -1,5 +1,5 @@
class Constraints: class Constraints:
def __init__(self, in_clk, in_rst_n, spi2csr0, led0): def __init__(self, in_clk, in_rst_n, spi2csr0, led0, sw0):
self.constraints = [] self.constraints = []
def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""): def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
self.constraints.append((signal, vec, pin, iostandard, extra,sch)) self.constraints.append((signal, vec, pin, iostandard, extra,sch))
@ -24,6 +24,9 @@ class Constraints:
# led0 # led0
add_vec(led0, ["U22", "U21", "V22", "V21", add_vec(led0, ["U22", "U21", "V22", "V21",
"W22" , "W21" , "Y22" , "Y21"]) "W22" , "W21" , "Y22" , "Y21"])
# sw0
add_vec(sw0, ["L22", "L21", "M22", "V12",
"W12" , "U12" , "U11" , "M2"])
def get_ios(self): def get_ios(self):
return set([c[0] for c in self.constraints]) return set([c[0] for c in self.constraints])

19
examples/de1/top.py
View File

@ -42,7 +42,7 @@ from migen.bank.description import *
import sys import sys
sys.path.append("../../") sys.path.append("../../")
from migScope import trigger, recorder from migScope import trigger, recorder, migIo
import spi2Csr import spi2Csr
from timings import * from timings import *
@ -74,10 +74,8 @@ RECORDER_ADDR = 0x0400
#============================================================================== #==============================================================================
def get(): def get():
# Control Reg # migIo
control_reg0 = RegisterField("control_reg0", 32, reset=0, access_dev=READ_ONLY) migIo0 = migIo.MigIo(8,"IO")
regs = [control_reg0]
bank0 = csrgen.Bank(regs,address=CONTROL_ADDR)
# Trigger # Trigger
term0 = trigger.Term(trig_width) term0 = trigger.Term(trig_width)
@ -92,7 +90,7 @@ def get():
# Csr Interconnect # Csr Interconnect
csrcon0 = csr.Interconnect(spi2csr0.csr, csrcon0 = csr.Interconnect(spi2csr0.csr,
[ [
bank0.interface, migIo0.bank.interface,
trigger0.bank.interface, trigger0.bank.interface,
recorder0.bank.interface recorder0.bank.interface
]) ])
@ -107,10 +105,11 @@ def get():
# Led # Led
led0 = Signal(BV(8)) led0 = Signal(BV(8))
comb += [ comb += [led0.eq(migIo0.o)]
led0.eq(control_reg0.field.r[:8])
]
#Switch
sw0 = Signal(BV(8))
comb += [migIo0.i.eq(sw0)]
# Dat / Trig Bus # Dat / Trig Bus
@ -135,7 +134,7 @@ def get():
] ]
frag = autofragment.from_local() frag = autofragment.from_local()
frag += Fragment(sync=sync,comb=comb) frag += Fragment(sync=sync,comb=comb)
cst = Constraints(in_clk, in_rst_n, spi2csr0, led0) cst = Constraints(in_clk, in_rst_n, spi2csr0, led0, sw0)
src_verilog, vns = verilog.convert(frag, src_verilog, vns = verilog.convert(frag,
cst.get_ios(), cst.get_ios(),
name="de1", name="de1",