remove crc since each crc is specific. It's probably better to adapt code for each case.
This commit is contained in:
Florent Kermarrec
Sebastien Bourdeauducq
parent
7471b2a152
commit
c7eba8f4c4
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@ -1,13 +0,0 @@
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from migen.fhdl.std import *
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from migen.genlib.crc import CRC32
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from migen.fhdl import verilog
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class Example(Module):
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def __init__(self, width):
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crc32 = CRC32(width)
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self.submodules += crc32
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self.ios = {crc32.reset, crc32.ce,
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crc32.d, crc32.value, crc32.error}
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example = Example(8)
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print(verilog.convert(example, example.ios))
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@ -1,171 +0,0 @@
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from migen.fhdl.std import *
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.record import *
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from migen.genlib.misc import chooser
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from migen.genlib.crc import *
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from migen.flow.actor import Sink, Source
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from migen.actorlib.fifo import SyncFIFO
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class CRCInserter(Module):
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"""CRC Inserter
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Append a CRC at the end of each packet.
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Parameters
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----------
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layout : layout
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Layout of the dataflow.
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Attributes
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----------
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sink : in
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Packets input without CRC.
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source : out
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Packets output with CRC.
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"""
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def __init__(self, crc_class, layout):
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self.sink = sink = Sink(layout)
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self.source = source = Source(layout)
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self.busy = Signal()
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###
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dw = flen(sink.d)
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crc = crc_class(dw)
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fsm = FSM(reset_state="IDLE")
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self.submodules += crc, fsm
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fsm.act("IDLE",
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crc.reset.eq(1),
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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NextState("COPY"),
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)
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)
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fsm.act("COPY",
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crc.ce.eq(sink.stb & source.ack),
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crc.d.eq(sink.d),
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Record.connect(sink, source),
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source.eop.eq(0),
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If(sink.stb & sink.eop & source.ack,
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NextState("INSERT"),
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)
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)
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ratio = crc.width//dw
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if ratio > 1:
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cnt = Signal(max=ratio, reset=ratio-1)
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cnt_done = Signal()
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fsm.act("INSERT",
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source.stb.eq(1),
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chooser(crc.value, cnt, source.d, reverse=True),
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If(cnt_done,
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source.eop.eq(1),
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If(source.ack, NextState("IDLE"))
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)
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)
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self.comb += cnt_done.eq(cnt == 0)
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self.sync += \
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If(fsm.ongoing("IDLE"),
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cnt.eq(cnt.reset)
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).Elif(fsm.ongoing("INSERT") & ~cnt_done,
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cnt.eq(cnt - source.ack)
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)
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else:
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fsm.act("INSERT",
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source.stb.eq(1),
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source.eop.eq(1),
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source.d.eq(crc.value),
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If(source.ack, NextState("IDLE"))
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)
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self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
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class CRC32Inserter(CRCInserter):
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def __init__(self, layout):
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CRCInserter.__init__(self, CRC32, layout)
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class CRCChecker(Module):
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"""CRC Checker
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Check CRC at the end of each packet.
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Parameters
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----------
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layout : layout
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Layout of the dataflow.
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Attributes
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----------
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sink : in
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Packets input with CRC.
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source : out
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Packets output without CRC and "error" set to 0
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on eop when CRC OK / set to 1 when CRC KO.
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"""
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def __init__(self, crc_class, layout):
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self.sink = sink = Sink(layout)
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self.source = source = Source(layout)
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self.busy = Signal()
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###
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dw = flen(sink.d)
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crc = crc_class(dw)
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self.submodules += crc
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ratio = crc.width//dw
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error = Signal()
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fifo = InsertReset(SyncFIFO(layout, ratio + 1))
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self.submodules += fifo
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fsm = FSM(reset_state="RESET")
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self.submodules += fsm
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fifo_in = Signal()
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fifo_out = Signal()
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fifo_full = Signal()
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self.comb += [
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fifo_full.eq(fifo.fifo.level == ratio),
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fifo_in.eq(sink.stb & (~fifo_full | fifo_out)),
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fifo_out.eq(source.stb & source.ack),
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Record.connect(sink, fifo.sink),
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fifo.sink.stb.eq(fifo_in),
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self.sink.ack.eq(fifo_in),
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source.stb.eq(sink.stb & fifo_full),
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source.sop.eq(fifo.source.sop),
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source.eop.eq(sink.eop),
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fifo.source.ack.eq(fifo_out),
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source.payload.eq(fifo.source.payload),
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source.error.eq(sink.error | crc.error),
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]
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fsm.act("RESET",
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crc.reset.eq(1),
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fifo.reset.eq(1),
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NextState("IDLE"),
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)
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fsm.act("IDLE",
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crc.d.eq(sink.d),
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If(sink.stb & sink.sop & sink.ack,
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crc.ce.eq(1),
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NextState("COPY")
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)
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)
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fsm.act("COPY",
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crc.d.eq(sink.d),
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If(sink.stb & sink.ack,
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crc.ce.eq(1),
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If(sink.eop,
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NextState("RESET")
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)
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)
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)
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self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
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class CRC32Checker(CRCChecker):
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def __init__(self, layout):
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CRCChecker.__init__(self, CRC32, layout)
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@ -1,114 +0,0 @@
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from collections import OrderedDict
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from migen.fhdl.std import *
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from migen.genlib.misc import optree
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class CRCEngine(Module):
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"""Cyclic Redundancy Check Engine
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Compute next CRC value from last CRC value and data input using
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an optimized asynchronous LFSR.
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Parameters
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----------
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dat_width : int
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Width of the data bus.
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width : int
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Width of the CRC.
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polynom : int
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Polynom of the CRC (ex: 0x04C11DB7 for IEEE 802.3 CRC)
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Attributes
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----------
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d : in
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Data input.
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last : in
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last CRC value.
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next :
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next CRC value.
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"""
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def __init__(self, dat_width, width, polynom):
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self.d = Signal(dat_width)
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self.last = Signal(width)
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self.next = Signal(width)
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###
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def _optimize_eq(l):
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"""
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Replace even numbers of XORs in the equation
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with an equivalent XOR
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"""
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d = OrderedDict()
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for e in l:
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if e in d:
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d[e] += 1
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else:
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d[e] = 1
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r = []
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for key, value in d.items():
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if value%2 != 0:
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r.append(key)
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return r
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# compute and optimize CRC's LFSR
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curval = [[("state", i)] for i in range(width)]
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for i in range(dat_width):
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feedback = curval.pop() + [("din", i)]
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for j in range(width-1):
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if (polynom & (1<<(j+1))):
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curval[j] += feedback
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curval[j] = _optimize_eq(curval[j])
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curval.insert(0, feedback)
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# implement logic
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for i in range(width):
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xors = []
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for t, n in curval[i]:
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if t == "state":
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xors += [self.last[n]]
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elif t == "din":
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xors += [self.d[n]]
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self.comb += self.next[i].eq(optree("^", xors))
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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class CRC32(Module):
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"""IEEE 802.3 CRC
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Implement an IEEE 802.3 CRC generator/checker.
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Parameters
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----------
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dat_width : int
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Width of the data bus.
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Attributes
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----------
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d : in
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Data input.
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value : out
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CRC value (used for generator).
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error : out
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CRC error (used for checker).
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"""
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width = 32
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polynom = 0x04C11DB7
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init = 2**width-1
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check = 0xC704DD7B
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def __init__(self, dat_width):
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self.d = Signal(dat_width)
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self.value = Signal(self.width)
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self.error = Signal()
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###
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self.submodules.engine = CRCEngine(dat_width, self.width, self.polynom)
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reg = Signal(self.width, reset=self.init)
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self.sync += reg.eq(self.engine.next)
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self.comb += [
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self.engine.d.eq(self.d),
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self.engine.last.eq(reg),
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self.value.eq(~reg[::-1]),
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self.error.eq(self.engine.next != self.check)
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]
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