link: add Scrambler and testbench
This commit is contained in:
Florent Kermarrec
parent
8062298668
commit
c810009387
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@ -55,11 +55,11 @@ class CRCEngine(Module):
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curval = [[("new", i)] for i in range(width)]
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for i in range(width):
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feedback = curval.pop()
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curval.insert(0, feedback)
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for j in range(1, width-1):
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if (polynom&(1<<j)):
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for j in range(width-1):
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if (polynom & (1<<(j+1))):
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curval[j] += feedback
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curval[j] = _optimize_eq(curval[j])
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curval.insert(0, feedback)
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# implement logic
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for i in range(width):
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@ -0,0 +1,67 @@
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from migen.fhdl.std import *
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from migen.genlib.misc import optree
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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class SATAScrambler(Module):
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"""SATA Scrambler
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Implement a SATA Scrambler
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Attributes
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----------
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value : out
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Scrambled value.
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"""
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def __init__(self):
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self.value = Signal(32)
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###
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context = Signal(16, reset=0xf0f6)
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next_value = Signal(32)
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self.sync += context.eq(next_value[16:32])
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# from SATA specification, if possible replace it
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# with a generic implementation using polynoms.
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lfsr_coefs = (
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(15, 13, 4, 0), #0
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(15, 14, 13, 5, 4, 1, 0),
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(14, 13, 6, 5, 4, 2,1, 0),
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(15, 14, 7, 6, 5, 3,2, 1),
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(13, 8, 7, 6, 3, 2, 0),
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(14, 9, 8, 7, 4, 3, 1),
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(15, 10, 9, 8, 5, 4, 2),
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(15, 13, 11, 10, 9, 6, 5, 4, 3, 0),
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(15, 14, 13, 12, 11, 10,7, 6, 5, 1, 0),
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(14, 12, 11, 8, 7, 6, 4, 2, 1, 0),
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(15, 13, 12, 9, 8, 7, 5, 3, 2, 1),
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(15, 14, 10, 9, 8, 6, 3, 2, 0),
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(13, 11, 10, 9, 7, 3, 1, 0),
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(14, 12, 11, 10, 8, 4, 2, 1),
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(15, 13, 12, 11, 9, 5, 3, 2),
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(15, 14, 12, 10, 6, 3, 0),
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(11, 7, 1, 0), #16
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(12, 8, 2, 1),
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(13, 9, 3, 2),
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(14, 10, 4, 3),
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(15, 11, 5, 4),
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(15, 13, 12, 6, 5, 4, 0),
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(15, 14, 7, 6, 5, 4, 1, 0),
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(13, 8, 7, 6, 5, 4, 2, 1, 0),
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(14, 9, 8,7, 6, 5, 3, 2, 1),
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(15, 10, 9, 8, 7, 6, 4, 3, 2),
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(15, 13, 11, 10, 9, 8, 7, 5, 3, 0),
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(15, 14, 13, 12, 11, 10, 9, 8, 6, 1, 0),
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(14, 12, 11, 10, 9, 7, 4, 2, 1, 0),
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(15, 13, 12, 11, 10, 8, 5, 3, 2, 1),
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(15, 14, 12, 11, 9, 6, 3, 2, 0),
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(12, 10, 7, 3, 1, 0),
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)
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for n, coefs in enumerate(lfsr_coefs):
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eq = [context[i] for i in coefs]
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self.comb += next_value[n].eq(optree("^", eq))
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self.comb += self.value.eq(next_value)
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@ -14,6 +14,7 @@ crc_tb:
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scrambler_tb:
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$(CC) $(CFLAGS) $(INC) -o scrambler scrambler.c
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./scrambler /> scrambler_ref
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$(CMD) scrambler_tb.py
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clean:
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rm crc crc_ref scrambler scrambler_ref
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@ -1,4 +1,50 @@
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// Adapted from SATA specification
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/****************************************************************************/
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/* */
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/* scramble.c */
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/* */
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/* This sample code generates the entire sequence of 65535 Dwords produced */
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/* by the scrambler defined in the Serial ATA specification. The */
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/* specification calls for an LFSR to generate a string of bits that will */
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/* be packaged into 32 bit Dwords to be XORed with the data Dwords. The */
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/* generator polynomial specified is: */
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/* 16 15 13 4 */
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/* G(x) = x + x + x + x + 1 */
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/* */
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/* Parallelized versions of the scrambler are initialized to a value */
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/* derived from the initialization value of 0xFFFF defined in the */
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/* specification. This implementation is initialized to 0xF0F6. Other */
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/* parallel implementations will have different initial values. The */
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/* important point is that the first Dword output of any implementation */
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/* must equal 0xC2D2768D. */
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/* This code does not represent an elegant solution for a C implementation, */
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/* but it does demonstrate a method of generating the sequence that can be */
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/* easily implemented in hardware. A block diagram of the circuit emulated */
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/* by this code is shown below. */
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/* */
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/* +-----------------------------------+ */
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/* | | */
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/* | | */
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/* | +---+ +---+ | */
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/* | | R | | * | | */
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/* +---->| e |----------+---->| M |----+----> Output(31 downto 16) */
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/* | g | | | 1 | */
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/* +---+ | +---+ */
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/* | */
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/* | +---+ */
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/* | | * | */
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/* +---->| M |---------> Output(15 downto 0) */
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/* | 2 | */
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/* +---+ */
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/* */
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/* The register shown in the block diagram is a 16 bit register. The two */
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/* boxes, *M1 and *M2, each represent a multiply by a 16 by 16 binary */
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/* matrix. A 16 by 16 matrix times a 16 bit vector yields a 16 bit vector. */
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/* The two vectors are the two halves of the 32 bit scrambler value. The */
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/* upper half of the scrambler value is stored back into the context */
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/* register to be used to generate the next value in the scrambler */
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/* */
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/****************************************************************************/
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#include <stdlib.h>
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#include <stdio.h>
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int main(int argc, char *argv[])
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@ -0,0 +1,54 @@
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from subprocess import check_output
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from migen.fhdl.std import *
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from lib.sata.std import *
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from lib.sata.link.scrambler import *
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def check(ref, res):
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shift = 0
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while((ref[0] != res[0]) and (len(res)>1)):
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res.pop(0)
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shift += 1
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length = min(len(ref), len(res))
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errors = 0
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for i in range(length):
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if ref.pop(0) != res.pop(0):
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errors += 1
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return shift, length, errors
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class TB(Module):
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def __init__(self):
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self.submodules.scrambler = SATAScrambler()
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def gen_simulation(self, selfp):
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# init CRC
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selfp.scrambler.ce = 1
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selfp.scrambler.reset = 1
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yield
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selfp.scrambler.reset = 0
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# get C code results
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ref = []
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f = open("scrambler_ref", "r")
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for l in f:
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ref.append(int(l, 16))
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f.close()
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# log results
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yield
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res = []
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for i in range(256):
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res.append(selfp.scrambler.value)
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yield
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for e in res:
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print("%08x" %e)
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# check results
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s, l, e = check(ref, res)
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print("shift "+ str(s) + " / length " + str(l) + " / errors " + str(e))
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if __name__ == "__main__":
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from migen.sim.generic import run_simulation
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run_simulation(TB(), ncycles=1000, vcd_name="my.vcd", keep_files=True)
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