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naxriscv/core: Cleanup ident.

This commit is contained in:
Florent Kermarrec 2022-04-08 18:53:46 +02:00
parent c4dba614a6
commit c834600a5a
1 changed files with 22 additions and 22 deletions
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44
litex/soc/cores/cpu/naxriscv/core.py
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@ -42,14 +42,14 @@ class NaxRiscv(CPU):
io_regions = {0x80000000: 0x80000000} # Origin, Length. io_regions = {0x80000000: 0x80000000} # Origin, Length.
# Default parameters. # Default parameters.
with_fpu = False with_fpu = False
with_rvc = False with_rvc = False
scala_args = [] scala_args = []
scala_files = ["gen.scala"] scala_files = ["gen.scala"]
netlist_name = None netlist_name = None
scala_paths = [] scala_paths = []
xlen = 32 xlen = 32
jtag_tap = False jtag_tap = False
jtag_instruction = False jtag_instruction = False
# ABI. # ABI.
@ -113,9 +113,9 @@ class NaxRiscv(CPU):
print(args.scala_args) print(args.scala_args)
if args.xlen: if args.xlen:
xlen = int(args.xlen) xlen = int(args.xlen)
NaxRiscv.xlen = xlen NaxRiscv.xlen = xlen
NaxRiscv.data_width = xlen NaxRiscv.data_width = xlen
NaxRiscv.gcc_triple = CPU_GCC_TRIPLE_RISCV64 NaxRiscv.gcc_triple = CPU_GCC_TRIPLE_RISCV64
NaxRiscv.linker_output_format = f"elf{xlen}-littleriscv" NaxRiscv.linker_output_format = f"elf{xlen}-littleriscv"
@ -323,21 +323,21 @@ class NaxRiscv(CPU):
self.jtag_tdo = Signal() self.jtag_tdo = Signal()
self.cpu_params.update( self.cpu_params.update(
i_jtag_tms=self.jtag_tms, i_jtag_tms = self.jtag_tms,
i_jtag_tck=self.jtag_tck, i_jtag_tck = self.jtag_tck,
i_jtag_tdi=self.jtag_tdi, i_jtag_tdi = self.jtag_tdi,
o_jtag_tdo=self.jtag_tdo, o_jtag_tdo = self.jtag_tdo,
) )
if NaxRiscv.jtag_instruction: if NaxRiscv.jtag_instruction:
self.jtag_clk = Signal() self.jtag_clk = Signal()
self.jtag_enable = Signal() self.jtag_enable = Signal()
self.jtag_capture = Signal() self.jtag_capture = Signal()
self.jtag_shift = Signal() self.jtag_shift = Signal()
self.jtag_update = Signal() self.jtag_update = Signal()
self.jtag_reset = Signal() self.jtag_reset = Signal()
self.jtag_tdo = Signal() self.jtag_tdo = Signal()
self.jtag_tdi = Signal() self.jtag_tdi = Signal()
self.cpu_params.update( self.cpu_params.update(
i_jtag_instruction_clk = self.jtag_clk, i_jtag_instruction_clk = self.jtag_clk,