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soc/cores/hyperbus/HyperRAMPHY: Add specific sampling clk_domain.

This commit is contained in:
Florent Kermarrec 2024-08-22 19:53:45 +02:00
parent c09d57d52d
commit c857f7845e
2 changed files with 23 additions and 17 deletions
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35
litex/soc/cores/hyperbus.py
View File

@ -23,7 +23,7 @@ from litex.soc.interconnect import wishbone
# HyperRAMPHY -------------------------------------------------------------------------------------- # HyperRAMPHY --------------------------------------------------------------------------------------
class HyperRAMPHY(LiteXModule): class HyperRAMPHY(LiteXModule):
def __init__(self, pads, data_width, clk_domain="sys"): def __init__(self, pads, data_width, clk_domain_o="sys", clk_domain_i="sys"):
self.rst = Signal() # i. self.rst = Signal() # i.
self.cs = Signal() # i. self.cs = Signal() # i.
self.dq_o = Signal(data_width) # i. self.dq_o = Signal(data_width) # i.
@ -38,25 +38,27 @@ class HyperRAMPHY(LiteXModule):
# Parameters. # Parameters.
# ---------- # ----------
self.clk_domain = clk_domain self.clk_domain_o = clk_domain_o
_sync = getattr(self.sync, clk_domain) self.clk_domain_i = clk_domain_i
_sync_o = getattr(self.sync, clk_domain_o)
_sync_i = getattr(self.sync, clk_domain_i)
# Rst. # Rst.
# ---- # ----
if hasattr(pads, "rst_n"): if hasattr(pads, "rst_n"):
_sync += pads.rst_n.eq(~self.rst) _sync_o += pads.rst_n.eq(~self.rst)
# CS_n. # CS_n.
# ----- # -----
pads.cs_n.reset = 2**len(pads.cs_n) - 1 pads.cs_n.reset = 2**len(pads.cs_n) - 1
_sync += pads.cs_n[0].eq(~self.cs) # Only supporting one Chip. _sync_o += pads.cs_n[0].eq(~self.cs) # Only supporting one Chip.
# Clk Gen. # Clk Gen.
# -------- # --------
clk = Signal() clk = Signal()
clk_d = Signal() clk_d = Signal()
clk_phase = Signal(2) clk_phase = Signal(2)
_sync += [ _sync_o += [
clk_phase.eq(0b00), clk_phase.eq(0b00),
If(self.cs, If(self.cs,
clk_phase.eq(clk_phase + 1) clk_phase.eq(clk_phase + 1)
@ -68,8 +70,8 @@ class HyperRAMPHY(LiteXModule):
0b11 : clk.eq(0), # 270°. 0b11 : clk.eq(0), # 270°.
}) })
] ]
self.specials += MultiReg(clk, clk_d, clk_domain, n={"sys": 0, "sys2x": 1}[clk_domain]) self.specials += MultiReg(clk, clk_d, clk_domain_o, n={"sys": 0, "sys2x": 1}[clk_domain_o])
self.comb += self.shift.eq(clk_phase[0] == 0 | (clk_domain == "sys2x")) self.comb += self.shift.eq(clk_phase[0] == 0 | (clk_domain_o == "sys2x"))
# Clk Out. # Clk Out.
# -------- # --------
@ -89,7 +91,8 @@ class HyperRAMPHY(LiteXModule):
dq = self.add_tristate(dq) dq = self.add_tristate(dq)
self.comb += dq.o.eq( self.dq_o) self.comb += dq.o.eq( self.dq_o)
self.comb += dq.oe.eq(self.dq_oe) self.comb += dq.oe.eq(self.dq_oe)
_sync += self.dq_i.eq(dq.i) # FIXME: Use phase-shifted Clk? _sync_i += self.dq_i.eq(dq.i)
#self.specials += MultiReg(dq.i, self.dq_i, clk_domain_i, n={"sys": 1, "sys2x_ps": 1}[clk_domain_i])
# RWDS. # RWDS.
# ----- # -----
@ -98,7 +101,8 @@ class HyperRAMPHY(LiteXModule):
rwds = self.add_tristate(pads.rwds) rwds = self.add_tristate(pads.rwds)
self.comb += rwds.o.eq( self.rwds_o) self.comb += rwds.o.eq( self.rwds_o)
self.comb += rwds.oe.eq( self.rwds_oe) self.comb += rwds.oe.eq( self.rwds_oe)
_sync += self.rwds_i.eq(rwds.i) # FIXME: Use phase-shifted Clk? _sync_i += self.rwds_i.eq(rwds.i)
#self.specials += MultiReg(rwds.i, self.rwds_i, clk_domain_i, n={"sys": 1, "sys2x_ps": 1}[clk_domain_i])
def add_tristate(self, pad): def add_tristate(self, pad):
class TristatePads: class TristatePads:
@ -155,10 +159,11 @@ class HyperRAM(LiteXModule):
# PHY. # PHY.
# ---- # ----
self.phy = phy = HyperRAMPHY( self.phy = phy = HyperRAMPHY(
pads = pads, pads = pads,
data_width = data_width, data_width = data_width,
clk_domain = {"4:1": "sys", "2:1": "sys2x"}[clk_ratio], clk_domain_o = {"4:1": "sys", "2:1": "sys2x"}[clk_ratio],
clk_domain_i = {"4:1": "sys", "2:1": "sys2x_ps"}[clk_ratio],
) )
# Config/Reg Interface. # Config/Reg Interface.
@ -429,7 +434,7 @@ class HyperRAM(LiteXModule):
self.status.fields.clk_ratio.eq({ self.status.fields.clk_ratio.eq({
"sys" : 4, "sys" : 4,
"sys2x": 2, "sys2x": 2,
}[self.phy.clk_domain]), }[self.phy.clk_domain_o]),
] ]
# Reg Interface. # Reg Interface.

5
test/test_hyperbus.py
View File

@ -86,8 +86,9 @@ class TestHyperBus(unittest.TestCase):
"sys2x" : hyperram_gen(dut), "sys2x" : hyperram_gen(dut),
} }
clocks = { clocks = {
"sys" : 4, "sys" : 4,
"sys2x" : 2, "sys2x" : 2,
"sys2x_ps" : 2,
} }
run_simulation(dut, generators, clocks, vcd_name="sim.vcd") run_simulation(dut, generators, clocks, vcd_name="sim.vcd")