soc/interconnect/stream: use new Converter/StrideConverter
This commit is contained in:
Florent Kermarrec
parent
8c272c1f6f
commit
c860581b86
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@ -29,11 +29,11 @@ class EndpointDescription:
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attributed.add(f[0])
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full_layout = [
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("payload", _make_m2s(self.payload_layout)),
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("param", _make_m2s(self.param_layout)),
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M),
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("eop", 1, DIR_M_TO_S)
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("eop", 1, DIR_M_TO_S),
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("payload", _make_m2s(self.payload_layout)),
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("param", _make_m2s(self.param_layout))
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]
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return full_layout
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@ -62,9 +62,8 @@ class Sink(Endpoint):
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class _FIFOWrapper(Module):
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def __init__(self, fifo_class, layout, depth):
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self.sink = Sink(layout)
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self.source = Source(layout)
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self.busy = Signal()
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self.sink = Endpoint(layout)
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self.source = Endpoint(layout)
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# # #
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@ -112,10 +111,10 @@ class AsyncFIFO(_FIFOWrapper):
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class Multiplexer(Module):
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def __init__(self, layout, n):
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self.source = Source(layout)
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self.source = Endpoint(layout)
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sinks = []
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for i in range(n):
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sink = Sink(layout)
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sink = Endpoint(layout)
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setattr(self, "sink"+str(i), sink)
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sinks.append(sink)
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self.sel = Signal(max=n)
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@ -130,10 +129,10 @@ class Multiplexer(Module):
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class Demultiplexer(Module):
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def __init__(self, layout, n):
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self.sink = Sink(layout)
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self.sink = Endpoint(layout)
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sources = []
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for i in range(n):
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source = Source(layout)
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source = Endpoint(layout)
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setattr(self, "source"+str(i), source)
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sources.append(source)
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self.sel = Signal(max=n)
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@ -145,6 +144,206 @@ class Demultiplexer(Module):
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cases[i] = self.sink.connect(source)
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self.comb += Case(self.sel, cases)
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class _UpConverter(Module):
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def __init__(self, nbits_from, nbits_to, ratio, reverse):
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self.sink = sink = Endpoint([("data", nbits_from)])
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self.source = source = Endpoint([("data", nbits_to),
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("valid_token_count", bits_for(ratio))])
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self.latency = 1
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# # #
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# control path
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demux = Signal(max=ratio)
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load_part = Signal()
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strobe_all = Signal()
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self.comb += [
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sink.ack.eq(~strobe_all | source.ack),
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source.stb.eq(strobe_all),
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load_part.eq(sink.stb & sink.ack)
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]
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demux_last = ((demux == (ratio - 1)) | sink.eop)
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self.sync += [
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If(source.ack, strobe_all.eq(0)),
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If(load_part,
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If(demux_last,
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demux.eq(0),
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strobe_all.eq(1)
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).Else(
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demux.eq(demux + 1)
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)
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),
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If(source.stb & source.ack,
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source.eop.eq(sink.eop),
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).Elif(sink.stb & sink.ack,
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source.eop.eq(sink.eop | source.eop)
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)
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]
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# data path
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cases = {}
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for i in range(ratio):
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n = ratio-i-1 if reverse else i
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cases[i] = source.data[n*nbits_from:(n+1)*nbits_from].eq(sink.data)
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self.sync += If(load_part, Case(demux, cases))
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# valid token count
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self.sync += If(load_part, source.valid_token_count.eq(demux + 1))
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class _DownConverter(Module):
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def __init__(self, nbits_from, nbits_to, ratio, reverse):
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self.sink = sink = Endpoint([("data", nbits_from)])
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self.source = source = Endpoint([("data", nbits_to),
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("valid_token_count", 1)])
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self.latency = 0
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# # #
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# control path
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mux = Signal(max=ratio)
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last = Signal()
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self.comb += [
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last.eq(mux == (ratio-1)),
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source.stb.eq(sink.stb),
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source.eop.eq(sink.eop & last),
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sink.ack.eq(last & source.ack)
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]
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self.sync += \
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If(source.stb & source.ack,
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If(last,
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mux.eq(0)
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).Else(
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mux.eq(mux + 1)
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)
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)
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# data path
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cases = {}
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for i in range(ratio):
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n = ratio-i-1 if reverse else i
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cases[i] = source.data.eq(sink.data[n*nbits_to:(n+1)*nbits_to])
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self.comb += Case(mux, cases).makedefault()
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# valid token count
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self.comb += source.valid_token_count.eq(last)
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class _IdentityConverter(Module):
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def __init__(self, nbits_from, nbits_to, ratio, reverse):
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self.sink = sink = Endpoint([("data", nbits_from)])
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self.source = source = Endpoint([("data", nbits_to),
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("valid_token_count", 1)])
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self.latency = 0
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# # #
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self.comb += [
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sink.connect(source),
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source.valid_token_count.eq(1)
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]
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def _get_converter_ratio(nbits_from, nbits_to):
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if nbits_from > nbits_to:
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converter_cls = _DownConverter
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if nbits_from % nbits_to:
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raise ValueError("Ratio must be an int")
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ratio = nbits_from//nbits_to
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elif nbits_from < nbits_to:
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converter_cls = _UpConverter
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if nbits_to % nbits_from:
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raise ValueError("Ratio must be an int")
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ratio = nbits_to//nbits_from
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else:
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converter_cls = _IdentityConverter
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ratio = 1
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return converter_cls, ratio
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class Converter(Module):
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def __init__(self, nbits_from, nbits_to, reverse=False,
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report_valid_token_count=False):
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self.cls, self.ratio = _get_converter_ratio(nbits_from, nbits_to)
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# # #
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converter = self.cls(nbits_from, nbits_to, self.ratio, reverse)
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self.submodules += converter
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self.latency = converter.latency
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self.sink = converter.sink
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if report_valid_token_count:
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self.source = converter.source
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else:
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self.source = Endpoint([("data", nbits_to)])
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self.comb += converter.source.connect(self.source,
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leave_out=set(["valid_token_count"]))
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class StrideConverter(Module):
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def __init__(self, description_from, description_to, reverse=False):
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self.sink = sink = Endpoint(description_from)
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self.source = source = Endpoint(description_to)
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# # #
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nbits_from = len(sink.payload.raw_bits())
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nbits_to = len(source.payload.raw_bits())
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converter = Converter(nbits_from, nbits_to, reverse)
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self.submodules += converter
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# cast sink to converter.sink (user fields --> raw bits)
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self.comb += [
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converter.sink.stb.eq(sink.stb),
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converter.sink.eop.eq(sink.eop),
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sink.ack.eq(converter.sink.ack)
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]
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if converter.cls == _DownConverter:
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ratio = converter.ratio
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for i in range(ratio):
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j = 0
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for name, width in source.description.payload_layout:
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src = getattr(sink, name)[i*width:(i+1)*width]
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dst = converter.sink.data[i*nbits_to+j:i*nbits_to+j+width]
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self.comb += dst.eq(src)
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j += width
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else:
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self.comb += converter.sink.data.eq(sink.payload.raw_bits())
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# cast converter.source to source (raw bits --> user fields)
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self.comb += [
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source.stb.eq(converter.source.stb),
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source.eop.eq(converter.source.eop),
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converter.source.ack.eq(source.ack)
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]
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if converter.cls == _UpConverter:
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ratio = converter.ratio
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for i in range(ratio):
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j = 0
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for name, width in sink.description.payload_layout:
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src = converter.source.data[i*nbits_from+j:i*nbits_from+j+width]
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dst = getattr(source, name)[i*width:(i+1)*width]
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self.comb += dst.eq(src)
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j += width
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else:
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self.comb += source.payload.raw_bits().eq(converter.source.data)
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# connect params
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if converter.latency == 0:
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self.comb += source.param.eq(sink.param)
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elif converter.latency == 1:
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self.sync += source.param.eq(sink.param)
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else:
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raise ValueError
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# TODO: clean up code below
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# XXX
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@ -351,99 +550,6 @@ class Pack(Module):
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]
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class Chunkerize(CombinatorialActor):
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def __init__(self, layout_from, layout_to, n, reverse=False):
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self.sink = Sink(layout_from)
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if isinstance(layout_to, EndpointDescription):
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layout_to = copy(layout_to)
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layout_to.payload_layout = pack_layout(layout_to.payload_layout, n)
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else:
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layout_to = pack_layout(layout_to, n)
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self.source = Source(layout_to)
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CombinatorialActor.__init__(self)
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# # #
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for i in range(n):
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chunk = n-i-1 if reverse else i
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for f in self.sink.description.payload_layout:
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src = getattr(self.sink, f[0])
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dst = getattr(getattr(self.source, "chunk"+str(chunk)), f[0])
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self.comb += dst.eq(src[i*len(src)//n:(i+1)*len(src)//n])
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for f in self.sink.description.param_layout:
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src = getattr(self.sink, f[0])
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dst = getattr(self.source, f[0])
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self.comb += dst.eq(src)
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class Unchunkerize(CombinatorialActor):
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def __init__(self, layout_from, n, layout_to, reverse=False):
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if isinstance(layout_from, EndpointDescription):
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fields = layout_from.payload_layout
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layout_from = copy(layout_from)
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layout_from.payload_layout = pack_layout(layout_from.payload_layout, n)
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else:
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fields = layout_from
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layout_from = pack_layout(layout_from, n)
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self.sink = Sink(layout_from)
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self.source = Source(layout_to)
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CombinatorialActor.__init__(self)
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# # #
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for i in range(n):
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chunk = n-i-1 if reverse else i
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for f in fields:
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src = getattr(getattr(self.sink, "chunk"+str(chunk)), f[0])
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dst = getattr(self.source, f[0])
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self.comb += dst[i*len(dst)//n:(i+1)*len(dst)//n].eq(src)
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for f in self.sink.description.param_layout:
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src = getattr(self.sink, f[0])
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dst = getattr(self.source, f[0])
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self.comb += dst.eq(src)
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class Converter(Module):
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def __init__(self, layout_from, layout_to, reverse=False):
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self.sink = Sink(layout_from)
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self.source = Source(layout_to)
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# # #
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width_from = len(self.sink.payload.raw_bits())
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width_to = len(self.source.payload.raw_bits())
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# downconverter
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if width_from > width_to:
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if width_from % width_to:
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raise ValueError
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ratio = width_from//width_to
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self.submodules.chunkerize = Chunkerize(layout_from, layout_to, ratio, reverse)
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self.submodules.unpack = Unpack(ratio, layout_to)
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self.submodules += Pipeline(self.sink,
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self.chunkerize,
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self.unpack,
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self.source)
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# upconverter
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elif width_to > width_from:
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if width_to % width_from:
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raise ValueError
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ratio = width_to//width_from
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self.submodules.pack = Pack(layout_from, ratio)
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self.submodules.unchunkerize = Unchunkerize(layout_from, ratio, layout_to, reverse)
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self.submodules += Pipeline(self.sink,
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self.pack,
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self.unchunkerize,
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self.source)
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# direct connection
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else:
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self.comb += self.sink.connect(self.source)
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class Pipeline(Module):
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def __init__(self, *modules):
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n = len(modules)
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