vexriscv: put debug bus directly on wishbone bus
By placing the VexRiscv debug bus on the Wishbone bus, the Etherbone core can access 32-bit values directly from the core. Additionally, both reading and writing are supported without the need to do a SYNC register as before. Additionally, the address of the Wishbone bus won't move around anymore, as it's fixed when doing `self.register_mem()`. Signed-off-by: Sean Cross <sean@xobs.io>
This commit is contained in:
Sean Cross
parent
20d6fcac61
commit
c87ca4f1c3
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@ -5,7 +5,6 @@ from migen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
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class VexRiscv(Module, AutoCSR):
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def __init__(self, platform, cpu_reset_address, variant=None):
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assert variant in (None, "debug"), "Unsupported variant %s" % variant
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@ -25,147 +24,71 @@ class VexRiscv(Module, AutoCSR):
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cpu_reset = Signal()
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cpu_args = {}
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cpu_filename = "VexRiscv-Debug.v"
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# Create four debug registers:
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# DEBUG_CORE: The contents of the debug core register
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# DEBUG_DATA: Write an instruction into the pipeline, or read the result.
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# DEBUG_REFRESH: Write 0x00 or 0x04 here to update either CORE or DATA
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# DEBUG_COUNT: An incrementing value that can be used to detect packet loss.
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# Updated on a successful WRITE to CORE, DATA, or REFRESH.
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self.debug_core = debug_core = CSRStorage(32, name="debug_core", write_from_dev=True)
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self.debug_data = debug_data = CSRStorage(32, name="debug_data", write_from_dev=True)
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self.debug_refresh = debug_refresh = CSRStorage(8, name="debug_refresh")
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self.debug_counter = debug_counter = CSRStatus(32, name="debug_counter")
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# # #
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debug_bus_cmd_payload_wr = Signal()
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debug_bus_cmd_payload_address = Signal(8)
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debug_bus_cmd_payload_data = Signal(32)
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debug_bus_cmd_ready = Signal()
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debug_bus_rsp_data = Signal(32)
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debug_start_cmd = Signal()
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debug_update_pending = Signal()
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debug_write_pending = Signal()
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debug_reset_out = Signal()
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debug_reset_counter = Signal(16)
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self.i_cmd_valid = Signal()
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self.i_cmd_payload_wr = Signal()
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self.i_cmd_payload_address = Signal(8)
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self.i_cmd_payload_data = Signal(32)
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self.o_cmd_ready = Signal()
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self.o_rsp_data = Signal(32)
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self.o_resetOut = Signal()
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# A bit to indicate whether we're REFRESHing the CORE or DATA register
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refreshing_data = Signal()
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self.transfer_complete = Signal()
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self.transfer_in_progress = Signal()
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self.transfer_wait_for_ack = Signal()
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self.debug_bus = wishbone.Interface()
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self.sync += [
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# If the core asserts reset_out, set debug_reset for 2**16 cycles.
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If(debug_reset_out,
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debug_reset_counter.eq(0),
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self.debug_reset.eq(1)
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).Elif(debug_reset_counter != (2**16-1),
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debug_reset_counter.eq(debug_reset_counter + 1)
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).Else(
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self.debug_reset.eq(0)
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),
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self.debug_bus.dat_r.eq(self.o_rsp_data),
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]
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# Reset the CPU if debug_reset is asserted and none of the
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# Wishbone buses are in use
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cpu_reset.eq((~i.cyc & ~d.cyc & ~d.stb & ~i.stb &
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self.debug_reset) | ResetSignal()),
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# If there's a Wishbone write on the CORE register, write to
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# debug register address 0.
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If(debug_core.re,
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debug_bus_cmd_payload_address.eq(0x00),
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debug_bus_cmd_payload_data.eq(debug_core.storage),
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debug_bus_cmd_payload_wr.eq(1),
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debug_start_cmd.eq(1),
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debug_write_pending.eq(1),
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debug_core.we.eq(0),
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debug_data.we.eq(0)
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# Or, if there's a write to the DATA register, write to
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# debug register address 4.
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).Elif(debug_data.re,
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debug_bus_cmd_payload_address.eq(0x04),
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debug_bus_cmd_payload_data.eq(debug_data.storage),
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debug_bus_cmd_payload_wr.eq(1),
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debug_start_cmd.eq(1),
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debug_write_pending.eq(1),
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debug_core.we.eq(0),
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debug_data.we.eq(0)
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# A write to the REFRESH register indicates which register
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# (DATA or CORE) we want to update from the CPU.
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).Elif(debug_refresh.re,
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If(debug_refresh.storage == 0,
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refreshing_data.eq(0),
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debug_bus_cmd_payload_address.eq(0)
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).Else(
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refreshing_data.eq(1),
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debug_bus_cmd_payload_address.eq(4)
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),
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# Data can be anything, since it's a "read"
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debug_bus_cmd_payload_data.eq(0),
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# Start a "Read" command with the "Write" bit set to 0
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debug_bus_cmd_payload_wr.eq(0),
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debug_start_cmd.eq(1),
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# The data will be ready when debug_bus_cmd_ready == 1,
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# so set the pending bit to look for it on future cycles.
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debug_update_pending.eq(1),
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debug_core.we.eq(0),
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debug_data.we.eq(0)
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# If the pending bit is set, check to see if the cmd_ready
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# bit from the debug bus is 1, indicating the CPU has finished
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# its operation and is in the idle state.
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).Elif(debug_update_pending,
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If(debug_bus_cmd_ready,
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debug_bus_cmd_payload_wr.eq(0),
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debug_update_pending.eq(0),
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debug_write_pending.eq(0),
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debug_start_cmd.eq(0),
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debug_counter.status.eq(debug_counter.status + 1),
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# Depending on whether we were asked to update the CORE
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# or DATA register, copy the response data to the correct CSR.
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If(~refreshing_data,
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debug_core.dat_w.eq(debug_bus_rsp_data),
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debug_core.we.eq(1),
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debug_data.we.eq(0)
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).Else(
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debug_data.dat_w.eq(debug_bus_rsp_data),
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debug_core.we.eq(0),
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debug_data.we.eq(1)
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)
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self.sync += [
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# CYC is held high for the duration of the transfer.
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# STB is kept high when the transfer finishes (write)
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# or the master is waiting for data (read), and stays
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# there until ACK, ERR, or RTY are asserted.
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If((self.debug_bus.stb & self.debug_bus.cyc)
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& (~self.transfer_in_progress)
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& (~self.transfer_complete)
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& (~self.transfer_wait_for_ack),
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self.i_cmd_payload_data.eq(self.debug_bus.dat_w),
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self.i_cmd_payload_address.eq((self.debug_bus.adr[0:6] << 2) | 0),
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self.i_cmd_payload_wr.eq(self.debug_bus.we),
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self.i_cmd_valid.eq(1),
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self.transfer_in_progress.eq(1),
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self.transfer_complete.eq(0),
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self.debug_bus.ack.eq(0)
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).Elif(self.transfer_in_progress,
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If(self.o_cmd_ready,
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self.i_cmd_valid.eq(0),
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self.i_cmd_payload_wr.eq(0),
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self.transfer_complete.eq(1),
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self.transfer_in_progress.eq(0)
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)
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# If there's a pending write to CORE or DATA, increment the
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# packet counter once the operation has finished.
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).Elif(debug_write_pending,
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If(debug_bus_cmd_ready,
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# When debug_bus_cmd_ready goes 1,
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debug_counter.status.eq(debug_counter.status + 1),
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debug_update_pending.eq(0),
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debug_write_pending.eq(0),
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debug_start_cmd.eq(0),
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debug_data.we.eq(0),
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debug_core.we.eq(0)
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)
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# Otherwise, ensure the Write Enable bits on the registers
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# are 0, so we're not constantly loading floating values.
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).Else(
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debug_core.we.eq(0),
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debug_data.we.eq(0)
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).Elif(self.transfer_complete,
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self.transfer_complete.eq(0),
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self.debug_bus.ack.eq(1),
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self.transfer_wait_for_ack.eq(1)
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).Elif(self.transfer_wait_for_ack & ~(self.debug_bus.stb & self.debug_bus.cyc),
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self.transfer_wait_for_ack.eq(0),
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self.debug_bus.ack.eq(0)
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)
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]
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cpu_reset.eq((~i.cyc & ~d.cyc & ~d.stb & ~i.stb &
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self.o_resetOut) | ResetSignal()),
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cpu_args.update({
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"i_debugReset": ResetSignal(),
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"i_debug_bus_cmd_valid": debug_start_cmd,
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"i_debug_bus_cmd_payload_wr": debug_bus_cmd_payload_wr,
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"i_debug_bus_cmd_payload_address": debug_bus_cmd_payload_address,
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"i_debug_bus_cmd_payload_data": debug_bus_cmd_payload_data,
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"o_debug_bus_cmd_ready": debug_bus_cmd_ready,
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"o_debug_bus_rsp_data": debug_bus_rsp_data,
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"o_debug_resetOut": debug_reset_out
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"i_debug_bus_cmd_valid": self.i_cmd_valid,
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"i_debug_bus_cmd_payload_wr": self.i_cmd_payload_wr,
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"i_debug_bus_cmd_payload_address": self.i_cmd_payload_address,
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"i_debug_bus_cmd_payload_data": self.i_cmd_payload_data,
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"o_debug_bus_cmd_ready": self.o_cmd_ready,
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"o_debug_bus_rsp_data": self.o_rsp_data,
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"o_debug_resetOut": self.o_resetOut
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})
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self.specials += Instance("VexRiscv",
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