Add initial changes to add IRQ support

In the waveform IRQ pending seems to be going high but the call to ISR() doesn't happen.

litex/soc/cores/cpu/ibex/core.py

@@ -124,6 +124,7 @@ class Ibex(CPU):
         self.dbus         = wishbone.Interface()
         self.periph_buses = [self.ibus, self.dbus]
         self.memory_buses = []
+        self.interrupt    = Signal(15)
 
         ibus = Record(obi_layout)
         dbus = Record(obi_layout)
@@ -170,7 +171,7 @@ class Ibex(CPU):
             i_irq_software_i = 0,
             i_irq_timer_i    = 0,
             i_irq_external_i = 0,
-            i_irq_fast_i     = 0,
+            i_irq_fast_i     = self.interrupt,
             i_irq_nm_i       = 0,
 
             # Debug.

litex/soc/cores/cpu/ibex/crt0.S

@@ -1,4 +1,6 @@
-#define MIE_MEIE  0x800
+#define MIE_MEIE  0x800 
+#define MIE_MFIE  0x7FFF0000
+#define MIE       (MIE_MEIE|MIE_MFIE)
 
   .global _start
 _start:
@@ -30,7 +32,7 @@ reset_vector:
   j 1b
 3:
   // enable external interrupts
-  li t0, MIE_MEIE
+  li t0, 0x7FFF0880
   csrs mie, t0
 
   call main

litex/soc/cores/cpu/ibex/csr-defs.h

@@ -0,0 +1,11 @@
+#ifndef CSR_DEFS__H
+#define CSR_DEFS__H
+
+#define CSR_MSTATUS_MIE 0x8
+
+#define CSR_IRQ_MASK 0xBC0
+#define CSR_IRQ_PENDING 0xFC0
+
+#define CSR_DCACHE_INFO 0xCC0
+
+#endif	/* CSR_DEFS__H */

litex/soc/cores/cpu/ibex/irq.h

@@ -1,4 +1,40 @@
 #ifndef __IRQ_H
 #define __IRQ_H
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <system.h>
+#include <generated/csr.h>
+
+static inline unsigned int irq_getie(void)
+{
+    return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
+}
+
+static inline void irq_setie(unsigned int ie)
+{
+	if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
+}
+
+static inline unsigned int irq_getmask(void)
+{
+    return 0; // FIXME
+}
+
+static inline void irq_setmask(unsigned int mask)
+{
+    // FIXME
+}
+
+static inline unsigned int irq_pending(void)
+{
+    return 0;// FIXME
+}
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __IRQ_H */

litex/soc/cores/cpu/ibex/system.h

@@ -1,6 +1,8 @@
 #ifndef __SYSTEM_H
 #define __SYSTEM_H
 
+#include <csr-defs.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -12,6 +14,28 @@ void flush_l2_cache(void);
 void busy_wait(unsigned int ms);
 void busy_wait_us(unsigned int us);
 
+#define csrr(reg) ({ unsigned long __tmp; \
+  asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+  __tmp; })
+
+#define csrw(reg, val) ({ \
+  if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
+	asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
+  else \
+	asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
+
+#define csrs(reg, bit) ({ \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+	asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
+  else \
+	asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
+
+#define csrc(reg, bit) ({ \
+  if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
+	asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
+  else \
+	asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
+
 #ifdef __cplusplus
 }
 #endif

litex/soc/software/bios/isr.c

@@ -68,7 +68,7 @@ void isr(void)
 		*((unsigned int *)PLIC_CLAIM) = claim;
 	}
 }
-#elif defined(__cv32e40p__)
+#elif defined(__cv32e40p__) || defined(__ibex__)
 
 #define FIRQ_OFFSET 16
 #define IRQ_MASK 0x7FFFFFFF
@@ -79,7 +79,41 @@ void isr(void)
 void isr(void)
 {
     unsigned int cause = csrr(mcause) & IRQ_MASK;
+	puts("isr");
+    if (csrr(mcause) & 0x80000000) {
+#ifndef UART_POLLING
+        if (cause == (UART_INTERRUPT+FIRQ_OFFSET)){
+            uart_isr();
+        }
+#endif
+    } else {
+#ifdef RISCV_TEST
+        int gp;
+        asm volatile ("mv %0, gp" : "=r"(gp));
+        printf("E %d\n", cause);
+        if (cause == INVINST) {
+            printf("Inv Instr\n");
+            for(;;);
+        }
+        if (cause == ECALL) {
+            printf("Ecall (gp: %d)\n", gp);
+            csrw(mepc, csrr(mepc)+4);
+        }
+#endif
+    }
+}
+#elif defined(__ibex__)
 
+#define FIRQ_OFFSET 16
+#define IRQ_MASK 0x7FFFFFFF
+#define INVINST 2
+#define ECALL 11
+#define RISCV_TEST
+
+void isr(void)
+{
+    unsigned int cause = csrr(mcause) & IRQ_MASK;
+	puts("isr");
     if (csrr(mcause) & 0x80000000) {
 #ifndef UART_POLLING
         if (cause == (UART_INTERRUPT+FIRQ_OFFSET)){