migen/genlib: add io.py to define generic I/O specials to be lowered by mibuild

mibuild/xilinx/common.py

@@ -5,6 +5,7 @@ from migen.fhdl.std import *
 from migen.fhdl.specials import SynthesisDirective
 from migen.genlib.cdc import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.genlib.io import *
 from mibuild.generic_platform import GenericPlatform
 from mibuild import tools
 
@@ -82,6 +83,15 @@ class XilinxAsyncResetSynchronizer:
 	def lower(dr):
 		return XilinxAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)
 
+class XilinxDifferentialInputImpl(Module):
+	def __init__(self, i_p, i_n, o):
+		self.specials += Instance("IBUFDS", i_I=i_p, i_IB=i_n, o_O=o)
+
+class XilinxDifferentialInput:
+	@staticmethod
+	def lower(dr):
+		return XilinxDifferentialInputImpl(dr.i_p, dr.i_n, dr.o)
+
 class XilinxGenericPlatform(GenericPlatform):
 	bitstream_ext = ".bit"
 
@@ -89,7 +99,8 @@ class XilinxGenericPlatform(GenericPlatform):
 		so = {
 			NoRetiming:					XilinxNoRetiming,
 			MultiReg:					XilinxMultiReg,
-			AsyncResetSynchronizer:		XilinxAsyncResetSynchronizer
+			AsyncResetSynchronizer:		XilinxAsyncResetSynchronizer,
+			DifferentialInput:			XilinxDifferentialInput,
 		}
 		so.update(special_overrides)
 		return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)

migen/genlib/io.py

@@ -0,0 +1,19 @@
+from migen.fhdl.std import *
+from migen.fhdl.specials import Special
+from migen.fhdl.tools import list_signals
+
+class DifferentialInput(Special):
+	def __init__(self, i_p, i_n, o):
+		Special.__init__(self)
+		self.i_p = i_p
+		self.i_n = i_n
+		self.o = o
+
+	def iter_expressions(self):
+		yield self, "i_p", SPECIAL_INPUT
+		yield self, "i_n", SPECIAL_INPUT
+		yield self, "o", SPECIAL_OUTPUT
+
+	@staticmethod
+	def lower(dr):
+		raise NotImplementedError("Attempted to use a reset synchronizer, but platform does not support them")