litesata: pep8 (E261, E271)

misoclib/mem/litesata/common.py

@@ -254,7 +254,7 @@ def command_rx_data_description(dw):
     return EndpointDescription(layout, packetized=True)
 
 # HDD
-logical_sector_size = 512 # constant since all HDDs use this
+logical_sector_size = 512  # constant since all HDDs use this
 
 
 def dwords2sectors(n):

misoclib/mem/litesata/core/link/scrambler.py

@@ -24,7 +24,7 @@ class Scrambler(Module):
         # XXX: from SATA specification, replace it with
         # a generic implementation using polynoms.
         lfsr_coefs = (
-            (15, 13, 4, 0), #0
+            (15, 13, 4, 0),  # 0
             (15, 14, 13, 5, 4, 1, 0),
             (14, 13, 6, 5, 4, 2, 1, 0),
             (15, 14, 7, 6, 5, 3, 2, 1),
@@ -41,7 +41,7 @@ class Scrambler(Module):
             (15, 13, 12, 11, 9, 5, 3, 2),
             (15, 14, 12, 10, 6, 3, 0),
 
-            (11, 7, 1, 0), #16
+            (11, 7, 1, 0),  # 16
             (12, 8, 2, 1),
             (13, 9, 3, 2),
             (14, 10, 4, 3),

misoclib/mem/litesata/example_designs/targets/bist.py

@@ -105,7 +105,7 @@ class BISTSoC(SoC, AutoCSR):
 
         # SATA PHY/Core/Frontend
         self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata"), "sata_gen2", clk_freq)
-        self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset) # XXX FIXME
+        self.comb += self.crg.reset.eq(self.sata_phy.ctrl.need_reset)  # XXX FIXME
         self.submodules.sata = LiteSATA(self.sata_phy, with_bist=True, with_bist_csr=True)
 
         # Status Leds

misoclib/mem/litesata/example_designs/test/bist.py

@@ -86,7 +86,7 @@ class LiteSATABISTIdentifyDriver:
             self.source_ack.write(1)
 
     def run(self, blocking=True):
-        self.read_fifo() # flush the fifo before we start
+        self.read_fifo()  # flush the fifo before we start
         self.start.write(1)
         if blocking:
             while (self.done.read() == 0):

misoclib/mem/litesata/frontend/bist.py

@@ -13,7 +13,7 @@ class LiteSATABISTGenerator(Module):
 
         self.done = Signal()
         self.aborted = Signal()
-        self.errors = Signal(32) # Note: Not used for writes
+        self.errors = Signal(32)  # Note: Not used for writes
 
         ###
 

misoclib/mem/litesata/phy/ctrl.py

@@ -91,7 +91,7 @@ class LiteSATAPHYCtrl(Module):
         )
         fsm.act("AWAIT_NO_RX_IDLE",
             trx.tx_idle.eq(0),
-            source.data.eq(0x4A4A4A4A), #D10.2
+            source.data.eq(0x4A4A4A4A),  # D10.2
             source.charisk.eq(0b0000),
             If(~trx.rx_idle,
                 NextState("AWAIT_ALIGN"),
@@ -101,7 +101,7 @@ class LiteSATAPHYCtrl(Module):
         )
         fsm.act("AWAIT_ALIGN",
             trx.tx_idle.eq(0),
-            source.data.eq(0x4A4A4A4A), #D10.2
+            source.data.eq(0x4A4A4A4A),  # D10.2
             source.charisk.eq(0b0000),
             trx.rx_align.eq(1),
             align_timeout.ce.eq(1),

misoclib/mem/litesata/phy/k7/trx.py

@@ -815,7 +815,7 @@ class K7LiteSATAPHYTRX(Module):
                     o_TXOUTCLK=self.txoutclk,
                     #o_TXOUTCLKFABRIC=,
                     #o_TXOUTCLKPCS=,
-                    i_TXOUTCLKSEL=0b11, #??
+                    i_TXOUTCLKSEL=0b11,  # ??
                     #o_TXRATEDONE=,
                 # Transmit Ports - TX Gearbox Ports
                     i_TXCHARISK=self.txcharisk,

misoclib/mem/litesata/test/hdd.py

@@ -152,7 +152,7 @@ class LinkTXPacket(LinkPacket):
 
 
 class LinkLayer(Module):
-    def  __init__(self, phy, debug=False, random_level=0):
+    def __init__(self, phy, debug=False, random_level=0):
         self.phy = phy
         self.debug = debug
         self.random_level = random_level