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boards/kc705: store bios in flash as it's done for others litex targets (we could use flash in custom designs)

This commit is contained in:
Florent Kermarrec 2017-02-10 09:29:50 +01:00
parent a3ef0fd53d
commit c98a90520e
1 changed files with 2 additions and 13 deletions
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15
litex/boards/targets/kc705.py
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@ -87,7 +87,8 @@ class BaseSoC(SoCSDRAM):
def __init__(self, toolchain="ise", **kwargs):
platform = kc705.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self, platform,
clk_freq=125*1000000, cpu_reset_address=0xaf0000,
clk_freq=125*1000000,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = _CRG(platform)
@ -98,18 +99,6 @@ class BaseSoC(SoCSDRAM):
self.register_sdram(self.ddrphy,
sdram_module.geom_settings, sdram_module.timing_settings)
if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.add_constant("SPIFLASH_PAGE_SIZE", 256)
self.add_constant("SPIFLASH_SECTOR_SIZE", 0x10000)
self.flash_boot_address = 0xb00000
self.register_rom(self.spiflash.bus)
class MiniSoC(BaseSoC):
csr_map = {