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rename shadow_address to shadow_base (more appropriate) and use | instead of + (as done in artiq)

This commit is contained in:
Florent Kermarrec 2015-05-02 16:57:32 +02:00
parent 145398d874
commit c98bd9fd79
5 changed files with 8 additions and 8 deletions
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2
misoclib/com/litepcie/example_designs/targets/dma.py
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@ -62,7 +62,7 @@ class PCIeDMASoC(SoC, AutoCSR):
clk_freq = 125*1000000
SoC.__init__(self, platform, clk_freq,
cpu_type="none",
shadow_address=0x00000000,
shadow_base=0x00000000,
with_csr=True, csr_data_width=32,
with_uart=False,
with_identifier=True,

8
misoclib/soc/__init__.py
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@ -39,7 +39,7 @@ class SoC(Module):
integrated_rom_size=0,
integrated_sram_size=4096,
integrated_main_ram_size=0,
shadow_address=0x80000000,
shadow_base=0x80000000,
with_csr=True, csr_data_width=8, csr_address_width=14,
with_uart=True, uart_baudrate=115200,
with_identifier=True,
@ -61,7 +61,7 @@ class SoC(Module):
self.with_identifier = with_identifier
self.shadow_address = shadow_address
self.shadow_base = shadow_base
self.with_csr = with_csr
self.csr_data_width = csr_data_width
@ -193,9 +193,9 @@ class SoC(Module):
data_width=self.csr_data_width, address_width=self.csr_address_width)
self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.add_csr_region(name, self.mem_map["csr"]+self.shadow_address+0x800*mapaddr, self.csr_data_width, csrs)
self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.add_csr_region(name + "_" + memory.name_override, self.mem_map["csr"]+self.shadow_address+0x800*mapaddr, self.csr_data_width, memory)
self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base, self.csr_data_width, memory)
# Interrupts
if hasattr(self.cpu_or_bridge, "interrupt"):

2
targets/kc705.py
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@ -127,6 +127,6 @@ class MiniSoC(BaseSoC):
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), platform.request("eth"), clk_freq=self.clk_freq)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
default_subtarget = BaseSoC

2
targets/mlabs_video.py
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@ -101,7 +101,7 @@ class MiniSoC(BaseSoC):
platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
def get_vga_dvi(platform):

2
targets/simple.py
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@ -43,6 +43,6 @@ class MiniSoC(BaseSoC):
interface="wishbone",
with_preamble_crc=False)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"]+self.shadow_address, 0x2000)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
default_subtarget = BaseSoC