integration/soc: Cosmetic cleanup pass.
This commit is contained in:
Florent Kermarrec
parent
6e23fb1d99
commit
c9ac5424f4
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@ -75,8 +75,8 @@ class SoCRegion:
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raise
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if (origin == 0) and (size == 2**bus.address_width):
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return lambda a : True
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origin >>= int(log2(bus.data_width//8)) # bytes to words aligned
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size >>= int(log2(bus.data_width//8)) # bytes to words aligned
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origin >>= int(log2(bus.data_width//8)) # bytes to words aligned.
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size >>= int(log2(bus.data_width//8)) # bytes to words aligned.
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return lambda a: (a[log2_int(size):] == (origin >> log2_int(size)))
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def __str__(self):
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@ -112,7 +112,7 @@ class SoCBusHandler(Module):
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self.logger = logging.getLogger(name)
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self.logger.info("Creating Bus Handler...")
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# Check Standard
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# Check Bus Standard.
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if standard not in self.supported_standard:
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self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
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colorer("Bus standard", color="red"),
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@ -120,7 +120,7 @@ class SoCBusHandler(Module):
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colorer(", ".join(self.supported_standard))))
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raise
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# Check Data Width
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# Check Bus Data Width.
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if data_width not in self.supported_data_width:
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self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
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colorer("Data Width", color="red"),
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@ -128,7 +128,7 @@ class SoCBusHandler(Module):
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colorer(", ".join(str(x) for x in self.supported_data_width))))
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raise
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# Check Address Width
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# Check Bus Address Width.
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if address_width not in self.supported_address_width:
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self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
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colorer("Address Width", color="red"),
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@ -148,7 +148,7 @@ class SoCBusHandler(Module):
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self.logger.info("{}-bit {} Bus, {}GiB Address Space.".format(
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colorer(data_width), colorer(standard), colorer(2**address_width/2**30)))
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# Adding reserved regions
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# Add reserved regions.
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self.logger.info("Adding {} Bus Regions...".format(colorer("reserved", color="cyan")))
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for name, region in reserved_regions.items():
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if isinstance(region, int):
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@ -164,9 +164,10 @@ class SoCBusHandler(Module):
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self.logger.error("{} already declared as Region:".format(colorer(name, color="red")))
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self.logger.error(self)
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raise
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# Check if SoCIORegion
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# Check if is SoCIORegion.
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if isinstance(region, SoCIORegion):
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self.io_regions[name] = region
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# Check for overlap with others IO regions.
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overlap = self.check_regions_overlap(self.io_regions)
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if overlap is not None:
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self.logger.error("IO Region {} between {} and {}:".format(
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@ -180,15 +181,16 @@ class SoCBusHandler(Module):
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colorer(name, color="underline"),
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colorer("added", color="green"),
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str(region)))
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# Check if SoCRegion
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# Check if is SoCRegion
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elif isinstance(region, SoCRegion):
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# If no origin specified, allocate region.
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# If no Origin specified, allocate Region.
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if region.origin is None:
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allocated = True
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region = self.alloc_region(name, region.size, region.cached)
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self.regions[name] = region
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# Else add region and check for overlaps.
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# Else add Region.
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else:
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# If Region is an IO Region is not cached.
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if not region.cached:
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if not self.check_region_is_io(region):
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self.logger.error("{} Region {}: {}.".format(
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@ -198,6 +200,7 @@ class SoCBusHandler(Module):
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self.logger.error(self)
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raise
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self.regions[name] = region
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# Check for overlab with others IO regions.
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overlap = self.check_regions_overlap(self.regions)
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if overlap is not None:
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self.logger.error("Region {} between {} and {}:".format(
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@ -220,27 +223,27 @@ class SoCBusHandler(Module):
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colorer("Cached" if cached else "IO"),
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colorer("0x{:08x}".format(size))))
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# Limit Search Regions
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# Limit Search Regions.
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if cached == False:
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search_regions = self.io_regions
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else:
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search_regions = {"main": SoCRegion(origin=0x00000000, size=2**self.address_width-1)}
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# Iterate on Search_Regions to find a Candidate
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# Iterate on Search_Regions to find a Candidate.
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for _, search_region in search_regions.items():
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origin = search_region.origin
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while (origin + size) < (search_region.origin + search_region.size_pow2):
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# Create a Candicate.
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candidate = SoCRegion(origin=origin, size=size, cached=cached)
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overlap = False
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# Check Candidate does not overlap with allocated existing regions
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# Check Candidate does not overlap with allocated existing regions.
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for _, allocated in self.regions.items():
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if self.check_regions_overlap({"0": allocated, "1": candidate}) is not None:
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origin = allocated.origin + allocated.size_pow2
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overlap = True
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break
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if not overlap:
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# If no overlap, the Candidate is selected
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# If no overlap, the Candidate is selected.
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return candidate
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self.logger.error("Not enough Address Space to allocate Region.")
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@ -283,7 +286,7 @@ class SoCBusHandler(Module):
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def add_adapter(self, name, interface, direction="m2s"):
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assert direction in ["m2s", "s2m"]
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# Data width conversion
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# Data width conversion.
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if interface.data_width != self.data_width:
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interface_cls = type(interface)
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converter_cls = {
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@ -300,7 +303,7 @@ class SoCBusHandler(Module):
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else:
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converted_interface = interface
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# Wishbone <-> AXILite bridging
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# Wishbone <-> AXILite bridging.
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main_bus_cls = {
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"wishbone": wishbone.Interface,
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"axi-lite": axi.AXILiteInterface,
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@ -321,7 +324,7 @@ class SoCBusHandler(Module):
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self.submodules += bridge
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if type(interface) != type(bridged_interface) or interface.data_width != bridged_interface.data_width:
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fmt = "{name} Bus {converted} from {frombus} {frombits}-bit to {tobus} {tobits}-bit."
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fmt = "{name} Bus {converted} from {from_bus} {from_bits}-bit to {to_bus} {to_bits}-bit."
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bus_names = {
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wishbone.Interface: "Wishbone",
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axi.AXILiteInterface: "AXI Lite",
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@ -329,10 +332,10 @@ class SoCBusHandler(Module):
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self.logger.info(fmt.format(
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name = colorer(name),
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converted = colorer("converted", color="cyan"),
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frombus = colorer(bus_names[type(interface)]),
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frombits = colorer(interface.data_width),
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tobus = colorer(bus_names[type(bridged_interface)]),
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tobits = colorer(bridged_interface.data_width)))
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from_bus = colorer(bus_names[type(interface)]),
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from_bits = colorer(interface.data_width),
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to_bus = colorer(bus_names[type(bridged_interface)]),
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to_bits = colorer(bridged_interface.data_width)))
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return bridged_interface
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def add_master(self, name=None, master=None):
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@ -403,7 +406,7 @@ class SoCBusHandler(Module):
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r = r[:-1]
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return r
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# SoCLocHandler --------------------------------------------------------------------------------------
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# SoCLocHandler ------------------------------------------------------------------------------------
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class SoCLocHandler(Module):
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# Creation -------------------------------------------------------------------------------------
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@ -487,7 +490,7 @@ class SoCCSRHandler(SoCLocHandler):
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self.logger = logging.getLogger("SoCCSRHandler")
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self.logger.info("Creating CSR Handler...")
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# Check Data Width
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# Check CSR Data Width.
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if data_width not in self.supported_data_width:
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self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
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colorer("Data Width", color="red"),
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@ -495,7 +498,7 @@ class SoCCSRHandler(SoCLocHandler):
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colorer(", ".join(str(x) for x in self.supported_data_width))))
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raise
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# Check Address Width
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# Check CSR Address Width.
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if address_width not in self.supported_address_width:
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self.logger.error("Unsupported {} {} supporteds: {:s}".format(
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colorer("Address Width", color="red"),
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@ -503,7 +506,7 @@ class SoCCSRHandler(SoCLocHandler):
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colorer(", ".join(str(x) for x in self.supported_address_width))))
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raise
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# Check Alignment
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# Check CSR Alignment.
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if alignment not in self.supported_alignment:
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self.logger.error("Unsupported {}: {} supporteds: {:s}".format(
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colorer("Alignment", color="red"),
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@ -517,7 +520,7 @@ class SoCCSRHandler(SoCLocHandler):
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colorer(data_width)))
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raise
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# Check Paging
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# Check CSR Paging.
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if paging not in self.supported_paging:
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self.logger.error("Unsupported {} 0x{}, supporteds: {:s}".format(
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colorer("Paging", color="red"),
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@ -525,7 +528,7 @@ class SoCCSRHandler(SoCLocHandler):
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colorer(", ".join("0x{:x}".format(x) for x in self.supported_paging))))
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raise
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# Check Ordering
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# Check CSR Ordering.
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if ordering not in self.supported_ordering:
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self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
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colorer("Ordering", color="red"),
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@ -533,7 +536,7 @@ class SoCCSRHandler(SoCLocHandler):
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colorer(", ".join("{}".format(x) for x in self.supported_ordering))))
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raise
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# Create CSR Handler
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# Create CSR Handler.
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self.data_width = data_width
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self.address_width = address_width
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self.alignment = alignment
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@ -549,7 +552,7 @@ class SoCCSRHandler(SoCLocHandler):
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colorer(self.ordering),
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colorer(self.n_locs)))
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# Adding reserved CSRs
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# Add reserved CSRs.
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self.logger.info("Adding {} CSRs...".format(colorer("reserved", color="cyan")))
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for name, n in reserved_csrs.items():
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self.add(name, n)
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@ -618,16 +621,16 @@ class SoCIRQHandler(SoCLocHandler):
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self.logger.info("Creating IRQ Handler...")
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self.enabled = False
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# Check IRQ Number
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# Check IRQ Number.
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if n_irqs > 32:
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self.logger.error("Unsupported IRQs number: {} supporteds: {:s}".format(
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colorer(n_irqs, color="red"), colorer("Up to 32", color="green")))
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raise
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# Create IRQ Handler
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# Create IRQ Handler.
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self.logger.info("IRQ Handler (up to {} Locations).".format(colorer(n_irqs)))
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# Adding reserved IRQs
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# Adding reserved IRQs.
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self.logger.info("Adding {} IRQs...".format(colorer("reserved", color="cyan")))
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for name, n in reserved_irqs.items():
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self.add(name, n)
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@ -657,11 +660,7 @@ class SoCIRQHandler(SoCLocHandler):
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# SoCController ------------------------------------------------------------------------------------
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class SoCController(Module, AutoCSR):
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def __init__(self,
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with_reset = True,
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with_scratch = True,
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with_errors = True):
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def __init__(self, with_reset=True, with_scratch=True, with_errors=True):
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if with_reset:
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self._reset = CSRStorage(1, description="""Any write to this register will reset the SoC.""")
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if with_scratch:
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@ -848,13 +847,15 @@ class SoC(Module):
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self.add_config("CSR_ALIGNMENT", self.csr.alignment)
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def add_cpu(self, name="vexriscv", variant="standard", cls=None, reset_address=None):
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# Check that CPU is supported.
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if name not in cpu.CPUS.keys():
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self.logger.error("{} CPU {}, supporteds: {}.".format(
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colorer(name),
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colorer("not supported", color="red"),
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colorer(", ".join(cpu.CPUS.keys()))))
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raise
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# Add CPU
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# Add CPU.
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if name == "external" and cls is None:
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self.logger.error("{} CPU requires {} to be specified.".format(
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colorer(name),
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@ -868,11 +869,13 @@ class SoC(Module):
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colorer(", ".join(cpu_cls.variants))))
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raise
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self.submodules.cpu = cpu_cls(self.platform, variant)
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# Update SoC with CPU constraints
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# Update SoC with CPU constraints.
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for n, (origin, size) in enumerate(self.cpu.io_regions.items()):
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self.bus.add_region("io{}".format(n), SoCIORegion(origin=origin, size=size, cached=False))
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self.mem_map.update(self.cpu.mem_map) # FIXME
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# Add Bus Masters/CSR/IRQs
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# Add Bus Masters/CSR/IRQs.
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if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000)):
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if reset_address is None:
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reset_address = self.mem_map["rom"]
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@ -886,7 +889,7 @@ class SoC(Module):
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self.irq.add(name, loc)
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self.add_config("CPU_HAS_INTERRUPT")
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# Create optional DMA Bus (for Cache Coherence)
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# Create optional DMA Bus (for Cache Coherence).
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if hasattr(self.cpu, "dma_bus"):
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self.submodules.dma_bus = SoCBusHandler(
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name = "SoCDMABusHandler",
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@ -898,17 +901,17 @@ class SoC(Module):
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self.dma_bus.add_slave("dma", slave=dma_bus, region=SoCRegion(origin=0x00000000, size=0x100000000)) # FIXME: covers lower 4GB only
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self.submodules += wishbone.Converter(dma_bus, self.cpu.dma_bus)
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# Connect SoCController's reset to CPU reset
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# Connect SoCController's reset to CPU reset.
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if hasattr(self, "ctrl"):
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if hasattr(self.ctrl, "reset"):
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self.comb += self.cpu.reset.eq(self.ctrl.reset)
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self.add_config("CPU_RESET_ADDR", reset_address)
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# Add CPU's SoC components (if any)
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# Add CPU's SoC components (if any).
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if hasattr(self.cpu, "add_soc_components"):
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self.cpu.add_soc_components(soc=self, soc_region_cls=SoCRegion) # FIXME: avoid passing SoCRegion.
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# Add constants
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# Add constants.
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self.add_config("CPU_TYPE", str(name))
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self.add_config("CPU_VARIANT", str(variant.split('+')[0]))
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self.add_constant("CONFIG_CPU_HUMAN_NAME", getattr(self.cpu, "human_name", "Unknown"))
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@ -1018,24 +1021,24 @@ class SoC(Module):
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masters = list(self.csr.masters.values()),
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slaves = self.csr_bankarray.get_buses())
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# Add CSRs regions
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# Add CSRs regions.
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for name, csrs, mapaddr, rmap in self.csr_bankarray.banks:
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self.csr.add_region(name, SoCCSRRegion(
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origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
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busword = self.csr.data_width,
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obj = csrs))
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# Add Memory regions
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# Add Memory regions.
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for name, memory, mapaddr, mmap in self.csr_bankarray.srams:
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self.csr.add_region(name + "_" + memory.name_override, SoCCSRRegion(
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origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
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busword = self.csr.data_width,
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obj = memory))
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# Sort CSR regions by origin
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# Sort CSR regions by origin.
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self.csr.regions = {k: v for k, v in sorted(self.csr.regions.items(), key=lambda item: item[1].origin)}
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# Add CSRs / Config items to constants
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# Add CSRs / Config items to constants.
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for name, constant in self.csr_bankarray.constants:
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self.add_constant(name + "_" + constant.name, constant.value.value)
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@ -1100,37 +1103,37 @@ class LiteXSoC(SoC):
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def add_uart(self, name, baudrate=115200, fifo_depth=16):
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from litex.soc.cores import uart
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# Stub / Stream
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# Stub / Stream.
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if name in ["stub", "stream"]:
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self.submodules.uart = uart.UART(tx_fifo_depth=0, rx_fifo_depth=0)
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if name == "stub":
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self.comb += self.uart.sink.ready.eq(1)
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# UARTBone / Bridge
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# UARTBone / Bridge.
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elif name in ["uartbone", "bridge"]:
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self.add_uartbone(baudrate=baudrate)
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# Crossover
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# Crossover.
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elif name in ["crossover"]:
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self.submodules.uart = uart.UARTCrossover(
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tx_fifo_depth = fifo_depth,
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rx_fifo_depth = fifo_depth)
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# Crossover + Bridge
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# Crossover + Bridge.
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elif name in ["crossover+bridge"]:
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self.add_uartbone(baudrate=baudrate)
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self.submodules.uart = uart.UARTCrossover(
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tx_fifo_depth = fifo_depth,
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rx_fifo_depth = fifo_depth)
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# Model/Sim
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# Model/Sim.
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elif name in ["model", "sim"]:
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self.submodules.uart_phy = uart.RS232PHYModel(self.platform.request("serial"))
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self.submodules.uart = uart.UART(self.uart_phy,
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tx_fifo_depth = fifo_depth,
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rx_fifo_depth = fifo_depth)
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# JTAG Atlantic
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# JTAG Atlantic.
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elif name in ["jtag_atlantic"]:
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from litex.soc.cores.jtag import JTAGAtlantic
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self.submodules.uart_phy = JTAGAtlantic()
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@ -1138,7 +1141,7 @@ class LiteXSoC(SoC):
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tx_fifo_depth = fifo_depth,
|
||||
rx_fifo_depth = fifo_depth)
|
||||
|
||||
# JTAG UART
|
||||
# JTAG UART.
|
||||
elif name in ["jtag_uart"]:
|
||||
from litex.soc.cores.jtag import JTAGPHY
|
||||
self.clock_domains.cd_sys_jtag = ClockDomain() # Run JTAG-UART in sys_jtag clock domain similar to
|
||||
|
|
@ -1148,7 +1151,7 @@ class LiteXSoC(SoC):
|
|||
tx_fifo_depth = fifo_depth,
|
||||
rx_fifo_depth = fifo_depth)
|
||||
|
||||
# USB ACM (with ValentyUSB core)
|
||||
# USB ACM (with ValentyUSB core).
|
||||
elif name in ["usb_acm"]:
|
||||
import valentyusb.usbcore.io as usbio
|
||||
import valentyusb.usbcore.cpu.cdc_eptri as cdc_eptri
|
||||
|
|
@ -1158,7 +1161,7 @@ class LiteXSoC(SoC):
|
|||
self.comb += self.cd_sys_usb.clk.eq(ClockSignal("sys")) # sys clock domain but with rst disconnected.
|
||||
self.submodules.uart = ClockDomainsRenamer("sys_usb")(cdc_eptri.CDCUsb(usb_iobuf))
|
||||
|
||||
# Classic UART
|
||||
# Classical UART.
|
||||
else:
|
||||
self.submodules.uart_phy = uart.UARTPHY(
|
||||
pads = self.platform.request(name),
|
||||
|
|
@ -1201,14 +1204,14 @@ class LiteXSoC(SoC):
|
|||
l2_cache_full_memory_we = True,
|
||||
**kwargs):
|
||||
|
||||
# Imports
|
||||
# Imports.
|
||||
from litedram.common import LiteDRAMNativePort
|
||||
from litedram.core import LiteDRAMCore
|
||||
from litedram.frontend.wishbone import LiteDRAMWishbone2Native
|
||||
from litedram.frontend.axi import LiteDRAMAXI2Native
|
||||
from litedram.frontend.bist import LiteDRAMBISTGenerator, LiteDRAMBISTChecker
|
||||
|
||||
# LiteDRAM core
|
||||
# LiteDRAM core.
|
||||
self.submodules.sdram = LiteDRAMCore(
|
||||
phy = phy,
|
||||
geom_settings = module.geom_settings,
|
||||
|
|
@ -1217,9 +1220,9 @@ class LiteXSoC(SoC):
|
|||
**kwargs)
|
||||
self.csr.add("sdram", use_loc_if_exists=True)
|
||||
|
||||
# Save SPD data to be able to verify it at runtime
|
||||
# Save SPD data to be able to verify it at runtime.
|
||||
if hasattr(module, "_spd_data"):
|
||||
# pack the data into words of bus width
|
||||
# Pack the data into words of bus width.
|
||||
bytes_per_word = self.bus.data_width // 8
|
||||
mem = [0] * ceil(len(module._spd_data) / bytes_per_word)
|
||||
for i in range(len(mem)):
|
||||
|
|
@ -1237,7 +1240,7 @@ class LiteXSoC(SoC):
|
|||
contents = mem,
|
||||
)
|
||||
|
||||
# LiteDRAM BIST
|
||||
# LiteDRAM BIST.
|
||||
if with_bist:
|
||||
self.submodules.sdram_generator = LiteDRAMBISTGenerator(self.sdram.crossbar.get_port())
|
||||
self.csr.add("sdram_generator")
|
||||
|
|
@ -1246,14 +1249,14 @@ class LiteXSoC(SoC):
|
|||
|
||||
if not with_soc_interconnect: return
|
||||
|
||||
# Compute/Check SDRAM size
|
||||
# Compute/Check SDRAM size.
|
||||
sdram_size = 2**(module.geom_settings.bankbits +
|
||||
module.geom_settings.rowbits +
|
||||
module.geom_settings.colbits)*phy.settings.databits//8
|
||||
if size is not None:
|
||||
sdram_size = min(sdram_size, size)
|
||||
|
||||
# Add SDRAM region
|
||||
# Add SDRAM region.
|
||||
self.bus.add_region("main_ram", SoCRegion(origin=origin, size=sdram_size))
|
||||
|
||||
# Add CPU's direct memory buses (if not already declared) ----------------------------------
|
||||
|
|
@ -1285,11 +1288,11 @@ class LiteXSoC(SoC):
|
|||
self.logger.info("Converting MEM data width: {} to {} via Wishbone".format(
|
||||
port.data_width,
|
||||
self.cpu.mem_axi.data_width))
|
||||
# FIXME: replace WB data-width converter with native AXI converter!!!
|
||||
# FIXME: Replace WB data-width converter with native AXI converter.
|
||||
mem_wb = wishbone.Interface(
|
||||
data_width = self.cpu.mem_axi.data_width,
|
||||
adr_width = 32-log2_int(self.cpu.mem_axi.data_width//8))
|
||||
# NOTE: AXI2Wishbone FSMs must be reset with the CPU!
|
||||
# FIXME: AXI2Wishbone FSMs must be reset with the CPU.
|
||||
mem_a2w = ResetInserter()(axi.AXI2Wishbone(
|
||||
axi = self.cpu.mem_axi,
|
||||
wishbone = mem_wb,
|
||||
|
|
@ -1349,7 +1352,7 @@ class LiteXSoC(SoC):
|
|||
self.submodules += wishbone.Converter(wb_sdram, litedram_wb)
|
||||
self.add_config("L2_SIZE", l2_cache_size)
|
||||
|
||||
# Wishbone Slave <--> LiteDRAM bridge
|
||||
# Wishbone Slave <--> LiteDRAM bridge.
|
||||
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(
|
||||
wishbone = litedram_wb,
|
||||
port = port,
|
||||
|
|
@ -1361,23 +1364,26 @@ class LiteXSoC(SoC):
|
|||
from liteeth.mac import LiteEthMAC
|
||||
from liteeth.phy.model import LiteEthPHYModel
|
||||
|
||||
# MAC
|
||||
# MAC.
|
||||
ethmac = LiteEthMAC(
|
||||
phy = phy,
|
||||
dw = 32,
|
||||
interface = "wishbone",
|
||||
endianness = self.cpu.endianness,
|
||||
with_preamble_crc = not software_debug,
|
||||
nrxslots = nrxslots,
|
||||
ntxslots = ntxslots)
|
||||
ntxslots = ntxslots,
|
||||
with_preamble_crc = not software_debug)
|
||||
# Use PHY's eth_tx/eth_rx clock domains.
|
||||
ethmac = ClockDomainsRenamer({
|
||||
"eth_tx": phy_cd + "_tx",
|
||||
"eth_rx": phy_cd + "_rx"})(ethmac)
|
||||
setattr(self.submodules, name, ethmac)
|
||||
ethmac_region_size = (ethmac.rx_slots.read()+ethmac.tx_slots.read())*ethmac.slot_size.read()
|
||||
# Compute Regions size and add it to the SoC.
|
||||
ethmac_region_size = (ethmac.rx_slots.read() + ethmac.tx_slots.read())*ethmac.slot_size.read()
|
||||
ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=ethmac_region_size, cached=False)
|
||||
self.bus.add_slave(name=name, slave=ethmac.bus, region=ethmac_region)
|
||||
self.csr.add(name, use_loc_if_exists=True)
|
||||
# Add IRQs (if enabled).
|
||||
if self.irq.enabled:
|
||||
self.irq.add(name, use_loc_if_exists=True)
|
||||
|
||||
|
|
@ -1389,6 +1395,7 @@ class LiteXSoC(SoC):
|
|||
self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
|
||||
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
|
||||
|
||||
# Dynamic IP (if enabled).
|
||||
if dynamic_ip:
|
||||
self.add_constant("ETH_DYNAMIC_IP")
|
||||
|
||||
|
|
@ -1414,13 +1421,14 @@ class LiteXSoC(SoC):
|
|||
mac_address = mac_address,
|
||||
ip_address = ip_address,
|
||||
clk_freq = self.clk_freq)
|
||||
# Use PHY's eth_tx/eth_rx clock domains.
|
||||
ethcore = ClockDomainsRenamer({
|
||||
"eth_tx": phy_cd + "_tx",
|
||||
"eth_rx": phy_cd + "_rx",
|
||||
"sys": phy_cd + "_rx"})(ethcore)
|
||||
self.submodules.ethcore = ethcore
|
||||
|
||||
# Clock domain renaming
|
||||
# Create Etherbone clock domain and run it from sys clock domain.
|
||||
self.clock_domains.cd_etherbone = ClockDomain("etherbone")
|
||||
self.comb += self.cd_etherbone.clk.eq(ClockSignal("sys"))
|
||||
self.comb += self.cd_etherbone.rst.eq(ResetSignal("sys"))
|
||||
|
|
@ -1483,14 +1491,16 @@ class LiteXSoC(SoC):
|
|||
|
||||
# Add SDCard -----------------------------------------------------------------------------------
|
||||
def add_sdcard(self, name="sdcard", mode="read+write", use_emulator=False, software_debug=False):
|
||||
assert mode in ["read", "write", "read+write"]
|
||||
# Imports
|
||||
# Imports.
|
||||
from litesdcard.emulator import SDEmulator
|
||||
from litesdcard.phy import SDPHY
|
||||
from litesdcard.core import SDCore
|
||||
from litesdcard.frontend.dma import SDBlock2MemDMA, SDMem2BlockDMA
|
||||
|
||||
# Emulator / Pads
|
||||
# Checks.
|
||||
assert mode in ["read", "write", "read+write"]
|
||||
|
||||
# Emulator / Pads.
|
||||
if use_emulator:
|
||||
sdemulator = SDEmulator(self.platform)
|
||||
self.submodules += sdemulator
|
||||
|
|
@ -1498,13 +1508,13 @@ class LiteXSoC(SoC):
|
|||
else:
|
||||
sdcard_pads = self.platform.request(name)
|
||||
|
||||
# Core
|
||||
# Core.
|
||||
self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device, self.clk_freq, cmd_timeout=10e-1, data_timeout=10e-1)
|
||||
self.submodules.sdcore = SDCore(self.sdphy)
|
||||
self.csr.add("sdphy", use_loc_if_exists=True)
|
||||
self.csr.add("sdcore", use_loc_if_exists=True)
|
||||
|
||||
# Block2Mem DMA
|
||||
# Block2Mem DMA.
|
||||
if "read" in mode:
|
||||
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
|
||||
self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
|
||||
|
|
@ -1513,7 +1523,7 @@ class LiteXSoC(SoC):
|
|||
dma_bus.add_master("sdblock2mem", master=bus)
|
||||
self.csr.add("sdblock2mem", use_loc_if_exists=True)
|
||||
|
||||
# Mem2Block DMA
|
||||
# Mem2Block DMA.
|
||||
if "write" in mode:
|
||||
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
|
||||
self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus, endianness=self.cpu.endianness)
|
||||
|
|
@ -1522,7 +1532,7 @@ class LiteXSoC(SoC):
|
|||
dma_bus.add_master("sdmem2block", master=bus)
|
||||
self.csr.add("sdmem2block", use_loc_if_exists=True)
|
||||
|
||||
# Interrupts
|
||||
# Interrupts.
|
||||
self.submodules.sdirq = EventManager()
|
||||
self.sdirq.card_detect = EventSourcePulse(description="SDCard has been ejected/inserted.")
|
||||
self.sdirq.block2mem_dma = EventSourcePulse(description="Block2Mem DMA terminated.")
|
||||
|
|
@ -1535,18 +1545,18 @@ class LiteXSoC(SoC):
|
|||
self.sdirq.mem2block_dma.trigger.eq(self.sdmem2block.irq),
|
||||
]
|
||||
|
||||
# Software Debug
|
||||
# Debug.
|
||||
if software_debug:
|
||||
self.add_constant("SDCARD_DEBUG")
|
||||
|
||||
# Add SATA -------------------------------------------------------------------------------------
|
||||
def add_sata(self, name="sata", phy=None, mode="read+write"):
|
||||
# Imports
|
||||
# Imports.
|
||||
from litesata.core import LiteSATACore
|
||||
from litesata.frontend.arbitration import LiteSATACrossbar
|
||||
from litesata.frontend.dma import LiteSATASector2MemDMA, LiteSATAMem2SectorDMA
|
||||
|
||||
# Checks
|
||||
# Checks.
|
||||
assert mode in ["read", "write", "read+write"]
|
||||
sata_clk_freqs = {
|
||||
"gen1": 75e6,
|
||||
|
|
@ -1556,13 +1566,13 @@ class LiteXSoC(SoC):
|
|||
sata_clk_freq = sata_clk_freqs[phy.gen]
|
||||
assert self.clk_freq >= sata_clk_freq/2 # FIXME: /2 for 16-bit data-width, add support for 32-bit.
|
||||
|
||||
# Core
|
||||
# Core.
|
||||
self.submodules.sata_core = LiteSATACore(phy)
|
||||
|
||||
# Crossbar
|
||||
# Crossbar.
|
||||
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
|
||||
|
||||
# Sector2Mem DMA
|
||||
# Sector2Mem DMA.
|
||||
if "read" in mode:
|
||||
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
|
||||
self.submodules.sata_sector2mem = LiteSATASector2MemDMA(
|
||||
|
|
@ -1573,7 +1583,7 @@ class LiteXSoC(SoC):
|
|||
dma_bus.add_master("sata_sector2mem", master=bus)
|
||||
self.csr.add("sata_sector2mem", use_loc_if_exists=True)
|
||||
|
||||
# Mem2Sector DMA
|
||||
# Mem2Sector DMA.
|
||||
if "write" in mode:
|
||||
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.address_width)
|
||||
self.submodules.sata_mem2sector = LiteSATAMem2SectorDMA(
|
||||
|
|
@ -1584,7 +1594,7 @@ class LiteXSoC(SoC):
|
|||
dma_bus.add_master("sata_mem2sector", master=bus)
|
||||
self.csr.add("sata_mem2sector", use_loc_if_exists=True)
|
||||
|
||||
# Timing constraints
|
||||
# Timing constraints.
|
||||
self.platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/sata_clk_freq)
|
||||
self.platform.add_period_constraint(self.sata_phy.crg.cd_sata_rx.clk, 1e9/sata_clk_freq)
|
||||
self.platform.add_false_path_constraints(
|
||||
|
|
@ -1594,24 +1604,25 @@ class LiteXSoC(SoC):
|
|||
|
||||
# Add PCIe -------------------------------------------------------------------------------------
|
||||
def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, with_msi=True):
|
||||
assert self.csr.data_width == 32
|
||||
assert not hasattr(self, f"{name}_endpoint")
|
||||
|
||||
# Imports
|
||||
from litepcie.core import LitePCIeEndpoint, LitePCIeMSI
|
||||
from litepcie.frontend.dma import LitePCIeDMA
|
||||
from litepcie.frontend.wishbone import LitePCIeWishboneMaster
|
||||
|
||||
# Endpoint
|
||||
# Checks.
|
||||
assert self.csr.data_width == 32
|
||||
assert not hasattr(self, f"{name}_endpoint")
|
||||
|
||||
# Endpoint.
|
||||
endpoint = LitePCIeEndpoint(phy, max_pending_requests=max_pending_requests)
|
||||
setattr(self.submodules, f"{name}_endpoint", endpoint)
|
||||
|
||||
# MMAP
|
||||
# MMAP.
|
||||
mmap = LitePCIeWishboneMaster(self.pcie_endpoint, base_address=self.mem_map["csr"])
|
||||
self.add_wb_master(mmap.wishbone)
|
||||
setattr(self.submodules, f"{name}_mmap", mmap)
|
||||
|
||||
# MSI
|
||||
# MSI.
|
||||
if with_msi:
|
||||
msi = LitePCIeMSI()
|
||||
setattr(self.submodules, f"{name}_msi", msi)
|
||||
|
|
@ -1619,7 +1630,7 @@ class LiteXSoC(SoC):
|
|||
self.comb += msi.source.connect(phy.msi)
|
||||
self.msis = {}
|
||||
|
||||
# DMAs
|
||||
# DMAs.
|
||||
for i in range(ndmas):
|
||||
assert with_msi
|
||||
dma = LitePCIeDMA(phy, endpoint,
|
||||
|
|
@ -1631,13 +1642,13 @@ class LiteXSoC(SoC):
|
|||
self.msis[f"{name.upper()}_DMA{i}_READER"] = dma.reader.irq
|
||||
self.add_constant("DMA_CHANNELS", ndmas)
|
||||
|
||||
# Map/Connect IRQs
|
||||
# Map/Connect IRQs.
|
||||
if with_msi:
|
||||
for i, (k, v) in enumerate(sorted(self.msis.items())):
|
||||
self.comb += msi.irqs[i].eq(v)
|
||||
self.add_constant(k + "_INTERRUPT", i)
|
||||
|
||||
# Timing constraints
|
||||
# Timing constraints.
|
||||
self.platform.add_false_path_constraints(self.crg.cd_sys.clk, phy.cd_pcie.clk)
|
||||
|
||||
# Add Video ColorBars Pattern ------------------------------------------------------------------
|
||||
|
|
|
|||
Loading…
Reference in New Issue