Merge pull request #149 from daveshah1/versa_trellis
Add trellis build option to versa_ecp5 and bring trellis support up to date
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commit
c9f9e237d9
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@ -68,8 +68,8 @@ class BaseSoC(SoCSDRAM):
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"ddrphy": 16,
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"ddrphy": 16,
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}
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}
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csr_map.update(SoCSDRAM.csr_map)
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csr_map.update(SoCSDRAM.csr_map)
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def __init__(self, **kwargs):
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def __init__(self, toolchain="diamond", **kwargs):
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platform = versa_ecp5.Platform(toolchain="diamond")
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platform = versa_ecp5.Platform(toolchain=toolchain)
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sys_clk_freq = int(50e6)
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sys_clk_freq = int(50e6)
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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integrated_rom_size=0x8000,
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@ -95,11 +95,13 @@ class BaseSoC(SoCSDRAM):
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def main():
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on ECP5")
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parser = argparse.ArgumentParser(description="LiteX SoC on ECP5")
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parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
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help='gateware toolchain to use, diamond (default) or trellis')
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builder_args(parser)
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builder_args(parser)
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soc_sdram_args(parser)
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soc_sdram_args(parser)
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args = parser.parse_args()
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args = parser.parse_args()
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soc = BaseSoC(**soc_sdram_argdict(args))
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soc = BaseSoC(toolchain=args.toolchain, **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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builder.build()
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@ -125,7 +125,7 @@ class LatticeTrellisToolchain:
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self.yosys_template = [
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self.yosys_template = [
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"{read_files}",
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"{read_files}",
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"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
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"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
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"synth_ecp5 -nomux -json {build_name}.json -top {build_name}",
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"synth_ecp5 -json {build_name}.json -top {build_name}",
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]
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]
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self.build_template = [
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self.build_template = [
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@ -189,9 +189,4 @@ class LatticeTrellisToolchain:
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# approach as the icestorm and use the fastest clock for timing
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# approach as the icestorm and use the fastest clock for timing
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# constraints.
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# constraints.
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def add_period_constraint(self, platform, clk, period):
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def add_period_constraint(self, platform, clk, period):
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new_freq = 1000.0/period
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platform.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
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if clk not in self.freq_constraints.keys():
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self.freq_constraints[clk] = new_freq
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else:
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raise ConstraintError("Period constraint already added to signal.")
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