Merge pull request #149 from daveshah1/versa_trellis

Add trellis build option to versa_ecp5 and bring trellis support up to date
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enjoy-digital 2019-02-25 19:26:07 +01:00 committed by GitHub
commit c9f9e237d9
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2 changed files with 7 additions and 10 deletions

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@ -68,8 +68,8 @@ class BaseSoC(SoCSDRAM):
"ddrphy": 16, "ddrphy": 16,
} }
csr_map.update(SoCSDRAM.csr_map) csr_map.update(SoCSDRAM.csr_map)
def __init__(self, **kwargs): def __init__(self, toolchain="diamond", **kwargs):
platform = versa_ecp5.Platform(toolchain="diamond") platform = versa_ecp5.Platform(toolchain=toolchain)
sys_clk_freq = int(50e6) sys_clk_freq = int(50e6)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000, integrated_rom_size=0x8000,
@ -95,11 +95,13 @@ class BaseSoC(SoCSDRAM):
def main(): def main():
parser = argparse.ArgumentParser(description="LiteX SoC on ECP5") parser = argparse.ArgumentParser(description="LiteX SoC on ECP5")
parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
help='gateware toolchain to use, diamond (default) or trellis')
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
args = parser.parse_args() args = parser.parse_args()
soc = BaseSoC(**soc_sdram_argdict(args)) soc = BaseSoC(toolchain=args.toolchain, **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build() builder.build()

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@ -125,7 +125,7 @@ class LatticeTrellisToolchain:
self.yosys_template = [ self.yosys_template = [
"{read_files}", "{read_files}",
"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0", "attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
"synth_ecp5 -nomux -json {build_name}.json -top {build_name}", "synth_ecp5 -json {build_name}.json -top {build_name}",
] ]
self.build_template = [ self.build_template = [
@ -189,9 +189,4 @@ class LatticeTrellisToolchain:
# approach as the icestorm and use the fastest clock for timing # approach as the icestorm and use the fastest clock for timing
# constraints. # constraints.
def add_period_constraint(self, platform, clk, period): def add_period_constraint(self, platform, clk, period):
new_freq = 1000.0/period platform.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
if clk not in self.freq_constraints.keys():
self.freq_constraints[clk] = new_freq
else:
raise ConstraintError("Period constraint already added to signal.")