Merge pull request #149 from daveshah1/versa_trellis

Add trellis build option to versa_ecp5 and bring trellis support up to date

litex/boards/targets/versa_ecp5.py

@@ -68,8 +68,8 @@ class BaseSoC(SoCSDRAM):
         "ddrphy":    16,
     }
     csr_map.update(SoCSDRAM.csr_map)
-    def __init__(self, **kwargs):
-        platform = versa_ecp5.Platform(toolchain="diamond")
+    def __init__(self, toolchain="diamond", **kwargs):
+        platform = versa_ecp5.Platform(toolchain=toolchain)
         sys_clk_freq = int(50e6)
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
                           integrated_rom_size=0x8000,
@@ -95,11 +95,13 @@ class BaseSoC(SoCSDRAM):
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on ECP5")
+    parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
+        help='gateware toolchain to use, diamond (default) or  trellis')
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()
 
-    soc = BaseSoC(**soc_sdram_argdict(args))
+    soc = BaseSoC(toolchain=args.toolchain, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()
 

litex/build/lattice/trellis.py

@@ -125,7 +125,7 @@ class LatticeTrellisToolchain:
         self.yosys_template = [
             "{read_files}",
             "attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
-            "synth_ecp5 -nomux -json {build_name}.json -top {build_name}",
+            "synth_ecp5 -json {build_name}.json -top {build_name}",
         ]
 
         self.build_template = [
@@ -189,9 +189,4 @@ class LatticeTrellisToolchain:
     # approach as the icestorm and use the fastest clock for timing
     # constraints.
     def add_period_constraint(self, platform, clk, period):
-        new_freq = 1000.0/period
-
-        if clk not in self.freq_constraints.keys():
-            self.freq_constraints[clk] = new_freq
-        else:
-            raise ConstraintError("Period constraint already added to signal.")
+        platform.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)