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add fpgaprog programmer

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Robert Jordens 2015-02-26 20:22:22 -07:00 committed by Sebastien Bourdeauducq
parent 5b5d2d15b8
commit ca52aa5b8c
1 changed files with 18 additions and 0 deletions
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18
mibuild/xilinx/programmer.py
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@ -45,6 +45,24 @@ class XC3SProg(GenericProgrammer):
flash_proxy = self.find_flash_proxy() flash_proxy = self.find_flash_proxy()
subprocess.call(["xc3sprog", "-v", "-c", self.cable, "-I"+flash_proxy, "{}:w:0x{:x}:BIN".format(data_file, address)]) subprocess.call(["xc3sprog", "-v", "-c", self.cable, "-I"+flash_proxy, "{}:w:0x{:x}:BIN".format(data_file, address)])
class FpgaProg(GenericProgrammer):
needs_bitreverse = False
def __init__(self, flash_proxy_basename=None):
GenericProgrammer.__init__(self, flash_proxy_basename)
def load_bitstream(self, bitstream_file):
subprocess.call(["fpgaprog", "-v", "-f", bitstream_file])
def flash(self, address, data_file):
if address != 0:
raise ValueError("fpga prog needs a main bitstream at address 0")
flash_proxy = self.find_flash_proxy()
subprocess.call(["fpgaprog", "-v", "-sa", "-r", "-b", flash_proxy,
"-f", data_file])
def _run_vivado(cmds): def _run_vivado(cmds):
with subprocess.Popen("vivado -mode tcl", stdin=subprocess.PIPE, shell=True) as process: with subprocess.Popen("vivado -mode tcl", stdin=subprocess.PIPE, shell=True) as process:
process.stdin.write(cmds.encode("ASCII")) process.stdin.write(cmds.encode("ASCII"))