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Restructure config flags for dcache/icache presence in Vex.

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Signed-off-by: Tim Callahan <tcal@google.com>
This commit is contained in:
Tim Callahan 2021-09-01 11:24:44 -07:00
parent 315fbe18cb
commit ca563dd5f3
2 changed files with 8 additions and 2 deletions
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6
litex/soc/cores/cpu/vexriscv/core.py
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@ -336,6 +336,12 @@ class VexRiscv(CPU, AutoCSR):
soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=soc_region_cls(
origin=soc.mem_map.get("vexriscv_debug"), size=0x100, cached=False))
base_variant = str(self.variant.split('+')[0])
if base_variant == "lite" or base_variant == "minimal":
soc.add_config("CPU_NO_DCACHE")
if base_variant == "minimal":
soc.add_config("CPU_NO_ICACHE")
def use_external_variant(self, variant_filename):
self.external_variant = True
self.platform.add_source(variant_filename)

4
litex/soc/cores/cpu/vexriscv/system.h
View file

@ -11,7 +11,7 @@ extern "C" {
__attribute__((unused)) static void flush_cpu_icache(void)
{
#if defined(CONFIG_CPU_VARIANT_MINIMAL)
#if defined(CONFIG_CPU_NO_ICACHE)
/* No instruction cache */
#else
asm volatile(
@ -27,7 +27,7 @@ __attribute__((unused)) static void flush_cpu_icache(void)
__attribute__((unused)) static void flush_cpu_dcache(void)
{
#if defined(CONFIG_CPU_VARIANT_MINIMAL) || defined(CONFIG_CPU_VARIANT_LITE)
#if defined(CONFIG_CPU_NO_DCACHE)
/* No data cache */
#else
asm volatile(".word(0x500F)\n");