json2renode: Add support for multicore builds
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@ -1,6 +1,6 @@
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#!/usr/bin/env python3
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"""
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Copyright (c) 2019-2021 Antmicro <www.antmicro.com>
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Copyright (c) 2019-2022 Antmicro <www.antmicro.com>
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Renode platform definition (repl) and script (resc) generator for LiteX SoC.
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@ -20,6 +20,8 @@ import argparse
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# and should not be generated automatically
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non_generated_mem_regions = ['ethmac', 'csr']
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# let's just fail if we access this prematurely
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number_of_cores = None
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def get_descriptor(csr, name, size=None):
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res = { 'base': csr['csr_bases'][name], 'constants': {} }
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@ -110,7 +112,7 @@ ethmac: Network.LiteX_Ethernet{} @ {{
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interrupt_name = '{}_interrupt'.format(name)
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if interrupt_name in csr['constants']:
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result += ' -> cpu@{}\n'.format(
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result += ' -> plic@{}\n'.format(
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csr['constants'][interrupt_name])
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result += """
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@ -204,6 +206,9 @@ def get_cpu_type(csr):
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return (kind, variant)
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def get_cpu_count(csr):
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config_cpu_count = csr['constants']['config_cpu_count']
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return config_cpu_count
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def generate_cpu(csr, time_provider):
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""" Generates definition of a CPU.
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@ -214,62 +219,68 @@ def generate_cpu(csr, time_provider):
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kind, variant = get_cpu_type(csr)
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if kind == 'vexriscv' or kind == 'vexriscv_smp':
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result = """
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cpu: CPU.VexRiscv @ sysbus
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cpu_string = """
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CPU.VexRiscv @ sysbus
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"""
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if variant == 'linux':
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result += """
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cpu_string += """
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cpuType: "rv32ima"
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privilegeArchitecture: PrivilegeArchitecture.Priv1_10
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"""
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elif variant in ["i", "im", "ima", "imac"]:
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result += """
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cpu_string += """
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cpuType: "rv32{}"
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""".format(variant)
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else:
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result += """
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cpu_string += """
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cpuType: "rv32im"
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"""
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if time_provider:
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result += """
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cpu_string += """
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timeProvider: {}
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""".format(time_provider)
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return result
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elif kind == 'picorv32':
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return """
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cpu: CPU.PicoRV32 @ sysbus
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cpu_string = """
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CPU.PicoRV32 @ sysbus
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cpuType: "rv32imc"
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"""
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elif kind == 'minerva':
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return """
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cpu: CPU.Minerva @ sysbus
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cpu_string = """
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CPU.Minerva @ sysbus
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"""
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elif kind == 'ibex':
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return """
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cpu: CPU.IbexRiscV32 @ sysbus
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cpu_string = """
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CPU.IbexRiscV32 @ sysbus
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"""
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elif kind == 'cv32e40p':
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result = """
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cpu: CPU.CV32E40P @ sysbus
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cpu_string = """
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CPU.CV32E40P @ sysbus
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"""
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if variant == 'standard':
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result += """
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cpu_string += """
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cpuType: "rv32imc"
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"""
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else:
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result += """
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cpu_string += """
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cpuType: "rv32imc"
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"""
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if time_provider:
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result += """
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cpu_string += """
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timeProvider: {}
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""".format(time_provider)
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return result
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else:
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raise Exception('Unsupported cpu type: {}'.format(kind))
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result = ''
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for cpu_id in range(0, number_of_cores):
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result += f"""
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cpu{cpu_id}: {cpu_string.strip()}
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hartId: {cpu_id}
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"""
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return result
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def generate_peripheral(csr, name, **kwargs):
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""" Generates definition of a peripheral.
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@ -298,7 +309,7 @@ def generate_peripheral(csr, name, **kwargs):
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for constant, val in peripheral['constants'].items():
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if 'ignored_constants' not in kwargs or constant not in kwargs['ignored_constants']:
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if constant == 'interrupt':
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result += ' -> cpu@{}\n'.format(val)
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result += ' -> plic@{}\n'.format(val)
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else:
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result += ' {}: {}\n'.format(constant, val)
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@ -418,11 +429,14 @@ def generate_clint(clint, frequency):
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result = """
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clint: IRQControllers.CoreLevelInterruptor @ {}
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frequency: {}
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[0, 1] -> cpu@[101, 100]
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numberOfTargets: {}
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""".format(generate_sysbus_registration(clint,
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skip_braces=True,
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skip_size=True),
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frequency)
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frequency, number_of_cores)
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for cpu_id in range(0, number_of_cores):
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result += f" [{2 * cpu_id}, {2 * cpu_id + 1}] -> cpu{cpu_id}@[101, 100]\n"
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return result
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@ -431,13 +445,16 @@ def generate_plic(plic):
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# TODO: this is configuration for linux-on-litex-vexriscv - add support for other CPU types
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result = """
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plic: IRQControllers.PlatformLevelInterruptController @ {}
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[0, 1] -> cpu@[11, 9]
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numberOfSources: 31
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numberOfContexts: 2
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numberOfContexts: {}
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prioritiesEnabled: false
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""".format(generate_sysbus_registration(plic,
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skip_braces=True,
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skip_size=True))
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skip_size=True),
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2 * number_of_cores)
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for cpu_id in range(0, number_of_cores):
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result += f" [{2 * cpu_id}, {2 * cpu_id + 1}] -> cpu{cpu_id}@[11, 9]\n"
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return result
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@ -521,7 +538,7 @@ peripherals_handlers = {
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},
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'interrupts': {
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# IRQ #100 in Renode's VexRiscv model is mapped to Machine Timer Interrupt
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'IRQ': lambda: 'cpu@100'
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'IRQ': lambda: 'cpu0@100'
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}
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},
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'ddrphy': {
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@ -591,7 +608,8 @@ def generate_repl(csr, etherbone_peripherals, autoalign):
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peripherals and memory regions
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"""
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result = ""
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global number_of_cores
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number_of_cores = get_cpu_count(csr)
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# RISC-V CPU in Renode requires memory region size
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# to be a multiple of 4KB - this is a known limitation
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@ -761,9 +779,10 @@ showAnalyzer sysbus.uart Antmicro.Renode.Analyzers.LoggingUartAnalyzer
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# load LiteX BIOS to ROM
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result += """
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sysbus LoadBinary @{} {}
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cpu PC {}
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""".format(args.bios_binary, rom_base, rom_base)
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""".format(args.bios_binary, hex(rom_base))
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for cpu_id in range(0, number_of_cores):
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result += f"cpu{cpu_id} PC {hex(rom_base)}\n"
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if args.tftp_ip:
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result += """
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