soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed)
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@ -184,6 +184,12 @@ class SoCCore(Module):
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# Add CPU buses as Wisbone masters
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for bus in self.cpu.buses:
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assert bus.data_width in [32, 64, 128]
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# Down Convert CPU buses to 32-bit if needed
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if bus.data_width != 32:
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dc_bus = wishbone.Interface()
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self.submodules += wishbone.Converter(bus, dc_bus)
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bus = dc_bus
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self.add_wb_master(bus)
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# Add CPU CSR (dynamic)
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@ -34,6 +34,8 @@ _layout = [
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class Interface(Record):
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def __init__(self, data_width=32, adr_width=30):
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self.data_width = data_width
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self.adr_width = adr_width
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Record.__init__(self, set_layout_parameters(_layout,
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adr_width=adr_width,
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data_width=data_width,
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