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soc/add_uartbone/add_jtagbone: improve phy naming and add uartbone_phy to CSR.

This commit is contained in:
Florent Kermarrec 2021-01-26 15:46:40 +01:00
parent 7479cbe71b
commit cafe0944f1
1 changed files with 5 additions and 4 deletions
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9
litex/soc/integration/soc.py
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@ -1169,16 +1169,17 @@ class LiteXSoC(SoC):
from litex.soc.cores import uart from litex.soc.cores import uart
if clk_freq is None: if clk_freq is None:
clk_freq = self.sys_clk_freq clk_freq = self.sys_clk_freq
self.submodules.phy = uart.UARTPHY(self.platform.request(name), clk_freq, baudrate) self.submodules.uartbone_phy = uart.UARTPHY(self.platform.request(name), clk_freq, baudrate)
self.submodules.uartbone = uart.UARTBone(phy=self.phy, clk_freq=clk_freq, cd=cd) self.csr.add("uartbone_phy")
self.submodules.uartbone = uart.UARTBone(phy=self.uartbone_phy, clk_freq=clk_freq, cd=cd)
self.bus.add_master(name="uartbone", master=self.uartbone.wishbone) self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
# Add JTAGbone --------------------------------------------------------------------------------- # Add JTAGbone ---------------------------------------------------------------------------------
def add_jtagbone(self): def add_jtagbone(self):
from litex.soc.cores import uart from litex.soc.cores import uart
from litex.soc.cores.jtag import JTAGPHY from litex.soc.cores.jtag import JTAGPHY
self.submodules.phy = JTAGPHY(device=self.platform.device) self.submodules.jtagbone_phy = JTAGPHY(device=self.platform.device)
self.submodules.jtagbone = uart.UARTBone(phy=self.phy, clk_freq=self.sys_clk_freq) self.submodules.jtagbone = uart.UARTBone(phy=self.jtagbone_phy, clk_freq=self.sys_clk_freq)
self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone) self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone)
# Add SDRAM ------------------------------------------------------------------------------------ # Add SDRAM ------------------------------------------------------------------------------------