soc/interconnect/stream: remove packetized parameter and use of sop
This commit is contained in:
Florent Kermarrec
parent
44a5b95281
commit
cb47373383
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@ -14,13 +14,12 @@ def _make_m2s(layout):
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class EndpointDescription:
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def __init__(self, payload_layout, param_layout=[], packetized=True):
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def __init__(self, payload_layout, param_layout=[]):
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self.payload_layout = payload_layout
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self.param_layout = param_layout
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self.packetized = packetized
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def get_full_layout(self):
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reserved = {"stb", "ack", "payload", "param", "sop", "eop", "description"}
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reserved = {"stb", "ack", "payload", "param", "eop", "description"}
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attributed = set()
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for f in self.payload_layout + self.param_layout:
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if f[0] in attributed:
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@ -33,13 +32,9 @@ class EndpointDescription:
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("payload", _make_m2s(self.payload_layout)),
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("param", _make_m2s(self.param_layout)),
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("stb", 1, DIR_M_TO_S),
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("ack", 1, DIR_S_TO_M)
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("ack", 1, DIR_S_TO_M),
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("eop", 1, DIR_M_TO_S)
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]
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if self.packetized:
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full_layout += [
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("sop", 1, DIR_M_TO_S),
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("eop", 1, DIR_M_TO_S)
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]
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return full_layout
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@ -74,9 +69,8 @@ class _FIFOWrapper(Module):
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# # #
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description = self.sink.description
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fifo_layout = [("payload", description.payload_layout)]
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if description.packetized:
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fifo_layout += [("sop", 1), ("eop", 1)]
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fifo_layout = [("payload", description.payload_layout),
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("eop", 1)]
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self.submodules.fifo = fifo_class(layout_len(fifo_layout), depth)
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fifo_in = Record(fifo_layout)
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@ -89,19 +83,14 @@ class _FIFOWrapper(Module):
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self.comb += [
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self.sink.ack.eq(self.fifo.writable),
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self.fifo.we.eq(self.sink.stb),
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fifo_in.eop.eq(self.sink.eop),
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fifo_in.payload.eq(self.sink.payload),
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self.source.stb.eq(self.fifo.readable),
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self.source.eop.eq(fifo_out.eop),
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self.source.payload.eq(fifo_out.payload),
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self.fifo.re.eq(self.source.ack)
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]
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if description.packetized:
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self.comb += [
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fifo_in.sop.eq(self.sink.sop),
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fifo_in.eop.eq(self.sink.eop),
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self.source.sop.eq(fifo_out.sop),
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self.source.eop.eq(fifo_out.eop)
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]
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class SyncFIFO(_FIFOWrapper):
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@ -199,14 +188,10 @@ class CombinatorialActor(BinaryActor):
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def build_binary_control(self, sink, source):
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self.comb += [
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source.stb.eq(sink.stb),
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source.eop.eq(sink.eop),
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sink.ack.eq(source.ack),
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self.busy.eq(0)
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]
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if sink.description.packetized:
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self.comb += [
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source.sop.eq(sink.sop),
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source.eop.eq(sink.eop)
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]
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class PipelinedActor(BinaryActor):
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@ -229,24 +214,15 @@ class PipelinedActor(BinaryActor):
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source.stb.eq(valid),
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self.busy.eq(busy)
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]
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if sink.description.packetized:
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sop = sink.stb & sink.sop
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eop = sink.stb & sink.eop
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for i in range(latency):
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sop_n = Signal()
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eop_n = Signal()
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self.sync += \
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If(self.pipe_ce,
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sop_n.eq(sop),
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eop_n.eq(eop)
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)
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sop = sop_n
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eop = eop_n
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self.comb += [
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source.eop.eq(eop),
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source.sop.eq(sop)
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]
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eop = sink.stb & sink.eop
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for i in range(latency):
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eop_n = Signal()
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self.sync += \
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If(self.pipe_ce,
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eop_n.eq(eop)
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)
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eop = eop_n
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self.comb += source.eop.eq(eop)
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class Buffer(PipelinedActor):
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@ -292,10 +268,8 @@ class Unpack(Module):
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# # #
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mux = Signal(max=n)
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first = Signal()
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last = Signal()
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self.comb += [
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first.eq(mux == 0),
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last.eq(mux == (n-1)),
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source.stb.eq(sink.stb),
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sink.ack.eq(last & source.ack)
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@ -320,11 +294,7 @@ class Unpack(Module):
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dst = getattr(self.source, f[0])
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self.comb += dst.eq(src)
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if description_from.packetized:
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self.comb += [
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source.sop.eq(sink.sop & first),
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source.eop.eq(sink.eop & last)
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]
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self.comb += source.eop.eq(sink.eop & last)
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class Pack(Module):
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@ -357,10 +327,7 @@ class Pack(Module):
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dst = getattr(self.source, f[0])
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self.sync += If(load_part, dst.eq(src))
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if description_to.packetized:
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demux_last = ((demux == (n - 1)) | sink.eop)
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else:
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demux_last = (demux == (n - 1))
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demux_last = ((demux == (n - 1)) | sink.eop)
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self.sync += [
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If(source.ack, strobe_all.eq(0)),
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@ -372,20 +339,14 @@ class Pack(Module):
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).Else(
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demux.eq(demux + 1)
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)
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),
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If(source.stb & source.ack,
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source.eop.eq(sink.eop),
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).Elif(sink.stb & sink.ack,
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source.eop.eq(sink.eop | source.eop)
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)
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]
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if description_to.packetized:
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self.sync += [
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If(source.stb & source.ack,
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source.sop.eq(sink.sop),
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source.eop.eq(sink.eop),
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).Elif(sink.stb & sink.ack,
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source.sop.eq(sink.sop | source.sop),
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source.eop.eq(sink.eop | source.eop)
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)
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]
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class Chunkerize(CombinatorialActor):
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def __init__(self, layout_from, layout_to, n, reverse=False):
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@ -18,18 +18,25 @@ def reverse_bytes(signal):
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class Status(Module):
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def __init__(self, endpoint):
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self.sop = sop = Signal()
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self.eop = eop =Signal()
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self.first = first = Signal(reset=1)
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self.eop = eop = Signal()
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self.ongoing = Signal()
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ongoing = Signal()
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self.comb += \
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If(endpoint.stb,
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sop.eq(endpoint.sop),
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eop.eq(endpoint.eop & endpoint.ack)
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)
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self.sync += ongoing.eq((sop | ongoing) & ~eop)
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self.comb += self.ongoing.eq((sop | ongoing) & ~eop)
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self.sync += ongoing.eq((endpoint.stb | ongoing) & ~eop)
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self.comb += self.ongoing.eq((endpoint.stb | ongoing) & ~eop)
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self.sync += [
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If(eop,
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first.eq(1)
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).Elif(endpoint.stb & endpoint.ack,
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first.eq(0)
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)
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]
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class Arbiter(Module):
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@ -72,11 +79,11 @@ class Dispatcher(Module):
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sel = Signal.like(self.sel)
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sel_ongoing = Signal.like(self.sel)
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self.sync += \
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If(status.sop,
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If(status.first,
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sel_ongoing.eq(self.sel)
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)
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self.comb += \
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If(status.sop,
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If(status.first,
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sel.eq(self.sel)
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).Else(
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sel.eq(sel_ongoing)
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@ -197,10 +204,9 @@ class Packetizer(Module):
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fsm.act("IDLE",
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sink.ack.eq(1),
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counter_reset.eq(1),
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If(sink.stb & sink.sop,
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If(sink.stb,
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sink.ack.eq(0),
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source.stb.eq(1),
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source.sop.eq(1),
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source.eop.eq(0),
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source.data.eq(self.header[:dw]),
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If(source.stb & source.ack,
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@ -212,7 +218,6 @@ class Packetizer(Module):
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if header_words != 1:
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fsm.act("SEND_HEADER",
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source.stb.eq(1),
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source.sop.eq(0),
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source.eop.eq(0),
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source.data.eq(header_reg[dw:2*dw]),
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If(source.stb & source.ack,
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@ -225,7 +230,6 @@ class Packetizer(Module):
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)
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fsm.act("COPY",
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source.stb.eq(sink.stb),
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source.sop.eq(0),
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source.eop.eq(sink.eop),
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source.data.eq(sink.data),
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source.error.eq(sink.error),
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@ -302,10 +306,7 @@ class Depacketizer(Module):
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no_payload = Signal()
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self.sync += \
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If(fsm.before_entering("COPY"),
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source.sop.eq(1),
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no_payload.eq(sink.eop)
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).Elif(source.stb & source.ack,
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source.sop.eq(0)
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)
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if hasattr(sink, "error"):
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@ -360,13 +361,6 @@ class Buffer(Module):
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self.submodules += fsm
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fsm.act("IDLE",
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If(cmd_fifo.source.stb,
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NextState("SEEK_SOP")
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)
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)
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fsm.act("SEEK_SOP",
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If(~data_fifo.source.sop,
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data_fifo.source.ack.eq(1)
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).Else(
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NextState("OUTPUT")
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)
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)
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@ -120,21 +120,17 @@ class PacketStreamer(Module):
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self.packet = self.packets.pop(0)
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if not self.packet.ongoing and not self.packet.done:
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selfp.source.stb = 1
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if self.source.description.packetized:
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selfp.source.sop = 1
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selfp.source.data = self.packet.pop(0)
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self.packet.ongoing = True
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elif selfp.source.stb == 1 and selfp.source.ack == 1:
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if self.source.description.packetized:
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selfp.source.sop = 0
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if len(self.packet) == 1:
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selfp.source.eop = 1
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if self.last_be is not None:
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selfp.source.last_be = self.last_be
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else:
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selfp.source.eop = 0
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if self.last_be is not None:
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selfp.source.last_be = 0
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if len(self.packet) == 1:
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selfp.source.eop = 1
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if self.last_be is not None:
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selfp.source.last_be = self.last_be
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else:
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selfp.source.eop = 0
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if self.last_be is not None:
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selfp.source.last_be = 0
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if len(self.packet) > 0:
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selfp.source.stb = 1
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selfp.source.data = self.packet.pop(0)
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@ -150,6 +146,7 @@ class PacketLogger(Module):
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# # #
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self.packet = Packet()
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self.first = True
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def receive(self):
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self.packet.done = False
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@ -159,16 +156,15 @@ class PacketLogger(Module):
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def do_simulation(self, selfp):
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selfp.sink.ack = 1
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if selfp.sink.stb:
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if self.sink.description.packetized:
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if selfp.sink.sop:
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self.packet = Packet()
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self.packet.append(selfp.sink.data)
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else:
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self.packet.append(selfp.sink.data)
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if selfp.sink.eop:
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self.packet.done = True
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if self.first:
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self.packet = Packet()
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self.packet.append(selfp.sink.data)
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self.first = False
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else:
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self.packet.append(selfp.sink.data)
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if selfp.sink.eop:
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self.packet.done = True
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self.first = True
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class AckRandomizer(Module):
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@ -158,10 +158,7 @@ class WishboneStreamingBridge(Module):
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self.comb += timer.wait.eq(~fsm.ongoing("IDLE"))
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if phy.sink.description.packetized:
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self.comb += [
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phy.sink.sop.eq((byte_counter == 0) & (word_counter == 0)),
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phy.sink.eop.eq((byte_counter == 3) & (word_counter == length - 1))
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]
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if hasattr(phy.sink, "length"):
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self.comb += phy.sink.length.eq(4*length)
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self.comb += phy.sink.eop.eq((byte_counter == 3) & (word_counter == length - 1))
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if hasattr(phy.sink, "length"):
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self.comb += phy.sink.length.eq(4*length)
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