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soc/interconnect/stream: remove packetized parameter and use of sop

This commit is contained in:
Florent Kermarrec 2016-03-15 22:58:48 +01:00
parent 44a5b95281
commit cb47373383
4 changed files with 60 additions and 112 deletions
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89
litex/soc/interconnect/stream.py
View File

@ -14,13 +14,12 @@ def _make_m2s(layout):
class EndpointDescription: class EndpointDescription:
def __init__(self, payload_layout, param_layout=[], packetized=True): def __init__(self, payload_layout, param_layout=[]):
self.payload_layout = payload_layout self.payload_layout = payload_layout
self.param_layout = param_layout self.param_layout = param_layout
self.packetized = packetized
def get_full_layout(self): def get_full_layout(self):
reserved = {"stb", "ack", "payload", "param", "sop", "eop", "description"} reserved = {"stb", "ack", "payload", "param", "eop", "description"}
attributed = set() attributed = set()
for f in self.payload_layout + self.param_layout: for f in self.payload_layout + self.param_layout:
if f[0] in attributed: if f[0] in attributed:
@ -33,13 +32,9 @@ class EndpointDescription:
("payload", _make_m2s(self.payload_layout)), ("payload", _make_m2s(self.payload_layout)),
("param", _make_m2s(self.param_layout)), ("param", _make_m2s(self.param_layout)),
("stb", 1, DIR_M_TO_S), ("stb", 1, DIR_M_TO_S),
("ack", 1, DIR_S_TO_M) ("ack", 1, DIR_S_TO_M),
("eop", 1, DIR_M_TO_S)
] ]
if self.packetized:
full_layout += [
("sop", 1, DIR_M_TO_S),
("eop", 1, DIR_M_TO_S)
]
return full_layout return full_layout
@ -74,9 +69,8 @@ class _FIFOWrapper(Module):
# # # # # #
description = self.sink.description description = self.sink.description
fifo_layout = [("payload", description.payload_layout)] fifo_layout = [("payload", description.payload_layout),
if description.packetized: ("eop", 1)]
fifo_layout += [("sop", 1), ("eop", 1)]
self.submodules.fifo = fifo_class(layout_len(fifo_layout), depth) self.submodules.fifo = fifo_class(layout_len(fifo_layout), depth)
fifo_in = Record(fifo_layout) fifo_in = Record(fifo_layout)
@ -89,19 +83,14 @@ class _FIFOWrapper(Module):
self.comb += [ self.comb += [
self.sink.ack.eq(self.fifo.writable), self.sink.ack.eq(self.fifo.writable),
self.fifo.we.eq(self.sink.stb), self.fifo.we.eq(self.sink.stb),
fifo_in.eop.eq(self.sink.eop),
fifo_in.payload.eq(self.sink.payload), fifo_in.payload.eq(self.sink.payload),
self.source.stb.eq(self.fifo.readable), self.source.stb.eq(self.fifo.readable),
self.source.eop.eq(fifo_out.eop),
self.source.payload.eq(fifo_out.payload), self.source.payload.eq(fifo_out.payload),
self.fifo.re.eq(self.source.ack) self.fifo.re.eq(self.source.ack)
] ]
if description.packetized:
self.comb += [
fifo_in.sop.eq(self.sink.sop),
fifo_in.eop.eq(self.sink.eop),
self.source.sop.eq(fifo_out.sop),
self.source.eop.eq(fifo_out.eop)
]
class SyncFIFO(_FIFOWrapper): class SyncFIFO(_FIFOWrapper):
@ -199,14 +188,10 @@ class CombinatorialActor(BinaryActor):
def build_binary_control(self, sink, source): def build_binary_control(self, sink, source):
self.comb += [ self.comb += [
source.stb.eq(sink.stb), source.stb.eq(sink.stb),
source.eop.eq(sink.eop),
sink.ack.eq(source.ack), sink.ack.eq(source.ack),
self.busy.eq(0) self.busy.eq(0)
] ]
if sink.description.packetized:
self.comb += [
source.sop.eq(sink.sop),
source.eop.eq(sink.eop)
]
class PipelinedActor(BinaryActor): class PipelinedActor(BinaryActor):
@ -229,24 +214,15 @@ class PipelinedActor(BinaryActor):
source.stb.eq(valid), source.stb.eq(valid),
self.busy.eq(busy) self.busy.eq(busy)
] ]
if sink.description.packetized: eop = sink.stb & sink.eop
sop = sink.stb & sink.sop for i in range(latency):
eop = sink.stb & sink.eop eop_n = Signal()
for i in range(latency): self.sync += \
sop_n = Signal() If(self.pipe_ce,
eop_n = Signal() eop_n.eq(eop)
self.sync += \ )
If(self.pipe_ce, eop = eop_n
sop_n.eq(sop), self.comb += source.eop.eq(eop)
eop_n.eq(eop)
)
sop = sop_n
eop = eop_n
self.comb += [
source.eop.eq(eop),
source.sop.eq(sop)
]
class Buffer(PipelinedActor): class Buffer(PipelinedActor):
@ -292,10 +268,8 @@ class Unpack(Module):
# # # # # #
mux = Signal(max=n) mux = Signal(max=n)
first = Signal()
last = Signal() last = Signal()
self.comb += [ self.comb += [
first.eq(mux == 0),
last.eq(mux == (n-1)), last.eq(mux == (n-1)),
source.stb.eq(sink.stb), source.stb.eq(sink.stb),
sink.ack.eq(last & source.ack) sink.ack.eq(last & source.ack)
@ -320,11 +294,7 @@ class Unpack(Module):
dst = getattr(self.source, f[0]) dst = getattr(self.source, f[0])
self.comb += dst.eq(src) self.comb += dst.eq(src)
if description_from.packetized: self.comb += source.eop.eq(sink.eop & last)
self.comb += [
source.sop.eq(sink.sop & first),
source.eop.eq(sink.eop & last)
]
class Pack(Module): class Pack(Module):
@ -357,10 +327,7 @@ class Pack(Module):
dst = getattr(self.source, f[0]) dst = getattr(self.source, f[0])
self.sync += If(load_part, dst.eq(src)) self.sync += If(load_part, dst.eq(src))
if description_to.packetized: demux_last = ((demux == (n - 1)) | sink.eop)
demux_last = ((demux == (n - 1)) | sink.eop)
else:
demux_last = (demux == (n - 1))
self.sync += [ self.sync += [
If(source.ack, strobe_all.eq(0)), If(source.ack, strobe_all.eq(0)),
@ -372,20 +339,14 @@ class Pack(Module):
).Else( ).Else(
demux.eq(demux + 1) demux.eq(demux + 1)
) )
),
If(source.stb & source.ack,
source.eop.eq(sink.eop),
).Elif(sink.stb & sink.ack,
source.eop.eq(sink.eop | source.eop)
) )
] ]
if description_to.packetized:
self.sync += [
If(source.stb & source.ack,
source.sop.eq(sink.sop),
source.eop.eq(sink.eop),
).Elif(sink.stb & sink.ack,
source.sop.eq(sink.sop | source.sop),
source.eop.eq(sink.eop | source.eop)
)
]
class Chunkerize(CombinatorialActor): class Chunkerize(CombinatorialActor):
def __init__(self, layout_from, layout_to, n, reverse=False): def __init__(self, layout_from, layout_to, n, reverse=False):

36
litex/soc/interconnect/stream_packet.py
View File

@ -18,18 +18,25 @@ def reverse_bytes(signal):
class Status(Module): class Status(Module):
def __init__(self, endpoint): def __init__(self, endpoint):
self.sop = sop = Signal() self.first = first = Signal(reset=1)
self.eop = eop =Signal() self.eop = eop = Signal()
self.ongoing = Signal() self.ongoing = Signal()
ongoing = Signal() ongoing = Signal()
self.comb += \ self.comb += \
If(endpoint.stb, If(endpoint.stb,
sop.eq(endpoint.sop),
eop.eq(endpoint.eop & endpoint.ack) eop.eq(endpoint.eop & endpoint.ack)
) )
self.sync += ongoing.eq((sop | ongoing) & ~eop) self.sync += ongoing.eq((endpoint.stb | ongoing) & ~eop)
self.comb += self.ongoing.eq((sop | ongoing) & ~eop) self.comb += self.ongoing.eq((endpoint.stb | ongoing) & ~eop)
self.sync += [
If(eop,
first.eq(1)
).Elif(endpoint.stb & endpoint.ack,
first.eq(0)
)
]
class Arbiter(Module): class Arbiter(Module):
@ -72,11 +79,11 @@ class Dispatcher(Module):
sel = Signal.like(self.sel) sel = Signal.like(self.sel)
sel_ongoing = Signal.like(self.sel) sel_ongoing = Signal.like(self.sel)
self.sync += \ self.sync += \
If(status.sop, If(status.first,
sel_ongoing.eq(self.sel) sel_ongoing.eq(self.sel)
) )
self.comb += \ self.comb += \
If(status.sop, If(status.first,
sel.eq(self.sel) sel.eq(self.sel)
).Else( ).Else(
sel.eq(sel_ongoing) sel.eq(sel_ongoing)
@ -197,10 +204,9 @@ class Packetizer(Module):
fsm.act("IDLE", fsm.act("IDLE",
sink.ack.eq(1), sink.ack.eq(1),
counter_reset.eq(1), counter_reset.eq(1),
If(sink.stb & sink.sop, If(sink.stb,
sink.ack.eq(0), sink.ack.eq(0),
source.stb.eq(1), source.stb.eq(1),
source.sop.eq(1),
source.eop.eq(0), source.eop.eq(0),
source.data.eq(self.header[:dw]), source.data.eq(self.header[:dw]),
If(source.stb & source.ack, If(source.stb & source.ack,
@ -212,7 +218,6 @@ class Packetizer(Module):
if header_words != 1: if header_words != 1:
fsm.act("SEND_HEADER", fsm.act("SEND_HEADER",
source.stb.eq(1), source.stb.eq(1),
source.sop.eq(0),
source.eop.eq(0), source.eop.eq(0),
source.data.eq(header_reg[dw:2*dw]), source.data.eq(header_reg[dw:2*dw]),
If(source.stb & source.ack, If(source.stb & source.ack,
@ -225,7 +230,6 @@ class Packetizer(Module):
) )
fsm.act("COPY", fsm.act("COPY",
source.stb.eq(sink.stb), source.stb.eq(sink.stb),
source.sop.eq(0),
source.eop.eq(sink.eop), source.eop.eq(sink.eop),
source.data.eq(sink.data), source.data.eq(sink.data),
source.error.eq(sink.error), source.error.eq(sink.error),
@ -302,10 +306,7 @@ class Depacketizer(Module):
no_payload = Signal() no_payload = Signal()
self.sync += \ self.sync += \
If(fsm.before_entering("COPY"), If(fsm.before_entering("COPY"),
source.sop.eq(1),
no_payload.eq(sink.eop) no_payload.eq(sink.eop)
).Elif(source.stb & source.ack,
source.sop.eq(0)
) )
if hasattr(sink, "error"): if hasattr(sink, "error"):
@ -360,13 +361,6 @@ class Buffer(Module):
self.submodules += fsm self.submodules += fsm
fsm.act("IDLE", fsm.act("IDLE",
If(cmd_fifo.source.stb, If(cmd_fifo.source.stb,
NextState("SEEK_SOP")
)
)
fsm.act("SEEK_SOP",
If(~data_fifo.source.sop,
data_fifo.source.ack.eq(1)
).Else(
NextState("OUTPUT") NextState("OUTPUT")
) )
) )

36
litex/soc/interconnect/stream_sim.py
View File

@ -120,21 +120,17 @@ class PacketStreamer(Module):
self.packet = self.packets.pop(0) self.packet = self.packets.pop(0)
if not self.packet.ongoing and not self.packet.done: if not self.packet.ongoing and not self.packet.done:
selfp.source.stb = 1 selfp.source.stb = 1
if self.source.description.packetized:
selfp.source.sop = 1
selfp.source.data = self.packet.pop(0) selfp.source.data = self.packet.pop(0)
self.packet.ongoing = True self.packet.ongoing = True
elif selfp.source.stb == 1 and selfp.source.ack == 1: elif selfp.source.stb == 1 and selfp.source.ack == 1:
if self.source.description.packetized: if len(self.packet) == 1:
selfp.source.sop = 0 selfp.source.eop = 1
if len(self.packet) == 1: if self.last_be is not None:
selfp.source.eop = 1 selfp.source.last_be = self.last_be
if self.last_be is not None: else:
selfp.source.last_be = self.last_be selfp.source.eop = 0
else: if self.last_be is not None:
selfp.source.eop = 0 selfp.source.last_be = 0
if self.last_be is not None:
selfp.source.last_be = 0
if len(self.packet) > 0: if len(self.packet) > 0:
selfp.source.stb = 1 selfp.source.stb = 1
selfp.source.data = self.packet.pop(0) selfp.source.data = self.packet.pop(0)
@ -150,6 +146,7 @@ class PacketLogger(Module):
# # # # # #
self.packet = Packet() self.packet = Packet()
self.first = True
def receive(self): def receive(self):
self.packet.done = False self.packet.done = False
@ -159,16 +156,15 @@ class PacketLogger(Module):
def do_simulation(self, selfp): def do_simulation(self, selfp):
selfp.sink.ack = 1 selfp.sink.ack = 1
if selfp.sink.stb: if selfp.sink.stb:
if self.sink.description.packetized: if self.first:
if selfp.sink.sop: self.packet = Packet()
self.packet = Packet() self.packet.append(selfp.sink.data)
self.packet.append(selfp.sink.data) self.first = False
else:
self.packet.append(selfp.sink.data)
if selfp.sink.eop:
self.packet.done = True
else: else:
self.packet.append(selfp.sink.data) self.packet.append(selfp.sink.data)
if selfp.sink.eop:
self.packet.done = True
self.first = True
class AckRandomizer(Module): class AckRandomizer(Module):

11
litex/soc/interconnect/wishbonebridge.py
View File

@ -158,10 +158,7 @@ class WishboneStreamingBridge(Module):
self.comb += timer.wait.eq(~fsm.ongoing("IDLE")) self.comb += timer.wait.eq(~fsm.ongoing("IDLE"))
if phy.sink.description.packetized: self.comb += phy.sink.eop.eq((byte_counter == 3) & (word_counter == length - 1))
self.comb += [
phy.sink.sop.eq((byte_counter == 0) & (word_counter == 0)), if hasattr(phy.sink, "length"):
phy.sink.eop.eq((byte_counter == 3) & (word_counter == length - 1)) self.comb += phy.sink.length.eq(4*length)
]
if hasattr(phy.sink, "length"):
self.comb += phy.sink.length.eq(4*length)