mirror of
https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
targets: add Lattice ECP3 versa
This commit is contained in:
parent
70f1f96fda
commit
cb4be52922
1 changed files with 17 additions and 0 deletions
17
targets/versa.py
Normal file
17
targets/versa.py
Normal file
|
@ -0,0 +1,17 @@
|
|||
from migen.fhdl.std import *
|
||||
from migen.bus import wishbone
|
||||
from migen.genlib.io import CRG
|
||||
|
||||
from misoclib.soc import SoC
|
||||
|
||||
class BaseSoC(SoC):
|
||||
default_platform = "versa"
|
||||
def __init__(self, platform, **kwargs):
|
||||
SoC.__init__(self, platform,
|
||||
clk_freq=100*1000000,
|
||||
with_rom=True,
|
||||
**kwargs)
|
||||
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n"))
|
||||
self.comb += platform.request("user_led", 0).eq(ResetSignal())
|
||||
|
||||
default_subtarget = BaseSoC
|
Loading…
Reference in a new issue