tools/litex_sim: Fix mem_map.
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@ -98,9 +98,7 @@ class Platform(SimPlatform):
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# Simulation SoC -----------------------------------------------------------------------------------
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# Simulation SoC -----------------------------------------------------------------------------------
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class SimSoC(SoCCore):
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class SimSoC(SoCCore):
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mem_map = {
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mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
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"spiflash" : 0x80000000,
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}
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def __init__(self,
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def __init__(self,
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with_sdram = False,
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with_sdram = False,
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with_ethernet = False,
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with_ethernet = False,
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