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ci/test_cpu: Install OpenRISC GCC toolchain in CI and add mor1kx to test_cpu.

This commit is contained in:
Florent Kermarrec 2021-10-26 15:36:07 +02:00
parent f6562195d5
commit cb9f0fb1b0
2 changed files with 13 additions and 5 deletions
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12
.github/workflows/ci.yml vendored
View File

@ -25,15 +25,18 @@ jobs:
- name: Install LiteX - name: Install LiteX
run: | run: |
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
python3 litex_setup.py init install --user python3 litex_setup.py --init --install --user
# Install RISC-V GCC # Install GCC Toolchains
- name: Install RISC-V GCC - name: Install GCC Toolchains
run: | run: |
wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
python3 litex_setup.py gcc python3 litex_setup.py --gcc=riscv
sudo mkdir /usr/local/riscv sudo mkdir /usr/local/riscv
sudo cp -r $PWD/../riscv64-*/* /usr/local/riscv sudo cp -r $PWD/../riscv64-*/* /usr/local/riscv
python3 litex_setup.py --gcc=openrisc
sudo mkdir /usr/local/openrisc
sudo cp -r $PWD/../openrisc-*/* /usr/local/openrisc
# Install Project # Install Project
- name: Install Project - name: Install Project
@ -43,4 +46,5 @@ jobs:
- name: Run Tests - name: Run Tests
run: | run: |
export PATH=/usr/local/riscv/bin:$PATH export PATH=/usr/local/riscv/bin:$PATH
export PATH=/usr/local/openrisc/bin:$PATH
python3 setup.py test python3 setup.py test

6
test/test_cpu.py
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@ -10,7 +10,7 @@ import sys
class TestCPU(unittest.TestCase): class TestCPU(unittest.TestCase):
def boot_test(self, cpu_type): def boot_test(self, cpu_type):
cmd = f'lxsim --cpu-type={cpu_type}' cmd = f'litex_sim --cpu-type={cpu_type}'
litex_prompt = [b'\033\[[0-9;]+mlitex\033\[[0-9;]+m>'] litex_prompt = [b'\033\[[0-9;]+mlitex\033\[[0-9;]+m>']
is_success = True is_success = True
with open("/tmp/test_boot_log", "wb") as result_file: with open("/tmp/test_boot_log", "wb") as result_file:
@ -34,6 +34,7 @@ class TestCPU(unittest.TestCase):
return is_success return is_success
# RISC-V CPUs.
def test_vexriscv(self): def test_vexriscv(self):
self.assertTrue(self.boot_test("vexriscv")) self.assertTrue(self.boot_test("vexriscv"))
@ -58,3 +59,6 @@ class TestCPU(unittest.TestCase):
def test_minerva(self): def test_minerva(self):
self.assertTrue(self.boot_test("minerva")) self.assertTrue(self.boot_test("minerva"))
# OpenRISC CPUs.
def test_mor1kx(self):
self.assertTrue(self.boot_test("mor1kx"))