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Fix VexiiRiscv

This commit is contained in:
Dolu1990 2024-07-18 11:32:07 +02:00
parent f687425cb1
commit cbe7413fee
1 changed files with 1 additions and 1 deletions
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2
litex/soc/cores/cpu/vexiiriscv/core.py
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@ -148,7 +148,7 @@ class VexiiRiscv(CPU):
vdir = get_data_mod("cpu", "vexiiriscv").data_location
ndir = os.path.join(vdir, "ext", "VexiiRiscv")
NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "7b16ef32", args.update_repo)
NaxRiscv.git_setup("VexiiRiscv", ndir, "https://github.com/SpinalHDL/VexiiRiscv.git", "dev", "36dad634", args.update_repo)
if not args.cpu_variant:
args.cpu_variant = "standard"