soc/intergration: Define platform/identifier as configs (and change PLATFORM to PLATFORM_NAME).
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@ -944,7 +944,6 @@ class SoC(LiteXModule, SoCCoreCompat):
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self.sys_clk_freq = int(sys_clk_freq) # Do conversion to int here to allow passing float to SoC.
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self.sys_clk_freq = int(sys_clk_freq) # Do conversion to int here to allow passing float to SoC.
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self.constants = {}
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self.constants = {}
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self.csr_regions = {}
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self.csr_regions = {}
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self.add_constant("platform", platform.name)
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# Set Top-Level to LiteXContext.
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# Set Top-Level to LiteXContext.
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LiteXContext.top = self
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LiteXContext.top = self
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@ -984,6 +983,8 @@ class SoC(LiteXModule, SoCCoreCompat):
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self.logger.info(self.irq)
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self.logger.info(self.irq)
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self.logger.info(colorer("-"*80, color="bright"))
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self.logger.info(colorer("-"*80, color="bright"))
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# SoC Configs ------------------------------------------------------------------------------
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self.add_config("PLATFORM_NAME", platform.name)
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self.add_config("CLOCK_FREQUENCY", int(sys_clk_freq))
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self.add_config("CLOCK_FREQUENCY", int(sys_clk_freq))
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# SoC Helpers ----------------------------------------------------------------------------------
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# SoC Helpers ----------------------------------------------------------------------------------
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@ -1473,7 +1474,7 @@ class LiteXSoC(SoC):
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else:
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else:
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self.add_config("BIOS_NO_BUILD_TIME")
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self.add_config("BIOS_NO_BUILD_TIME")
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self.add_module(name=name, module=Identifier(identifier))
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self.add_module(name=name, module=Identifier(identifier))
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self.add_constant(name, identifier)
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self.add_config(name, identifier)
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# Add UART -------------------------------------------------------------------------------------
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# Add UART -------------------------------------------------------------------------------------
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def add_uart(self, name="uart", uart_name="serial", baudrate=115200, fifo_depth=16):
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def add_uart(self, name="uart", uart_name="serial", baudrate=115200, fifo_depth=16):
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