cores/cpu/zynq7000: fix axi hp slave registration

2020-11-03 00:55:16 +01:00 · 2020-11-03 00:55:16 +01:00 · cc652dda77
parent 081d883421
commit cc652dda77
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/cpu/zynq7000/core.py
+++ b/litex/soc/cores/cpu/zynq7000/core.py
@ -215,7 +215,7 @@ class Zynq7000(CPU):
        assert len(self.axi_hp_slaves) < 4
        n       = len(self.axi_hp_slaves)
        axi_hpn = axi.AXIInterface(data_width=64, address_width=32, id_width=6)
-        self.axi_hp_masters.append(axi_hpn)
+        self.axi_hp_slaves.append(axi_hpn)
        self.cpu_params.update({
            # AXI HP0 clk
            f"i_S_AXI_HP{n}_ACLK"    : ClockSignal("ps7"),