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cores/spi_flash: Add USSPIFlash based on S7SPIFlash.

This commit is contained in:
Florent Kermarrec 2023-01-25 10:03:00 +01:00
parent 03342065c3
commit cc91f2ee3a
1 changed files with 26 additions and 1 deletions
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27
litex/soc/cores/spi_flash.py
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@ -1,7 +1,7 @@
# #
# This file is part of LiteX. # This file is part of LiteX.
# #
# Copyright (c) 2014-2018 Florent Kermarrec <florent@enjoy-digital.fr> # Copyright (c) 2014-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
from migen import * from migen import *
@ -36,6 +36,31 @@ class S7SPIFlash(Module, AutoCSR):
spi.pads.miso.eq(pads.miso) spi.pads.miso.eq(pads.miso)
] ]
# Xilinx Ultrascale FPGAs SPI Flash (non-memory-mapped) --------------------------------------------
class USSPIFlash(Module, AutoCSR):
def __init__(self, pads, sys_clk_freq, spi_clk_freq=25e6):
self.submodules.spi = spi = SPIMaster(None, 40, sys_clk_freq, spi_clk_freq)
self.specials += Instance("STARTUPE3",
i_GSR = 0,
i_GTS = 0,
i_KEYCLEARB = 0,
i_PACK = 0,
i_USRCCLKO = spi.pads.clk,
i_USRCCLKTS = 0,
i_USRDONEO = 1,
i_USRDONETS = 1
)
if hasattr(pads, "vpp"):
pads.vpp.reset = 1
if hasattr(pads, "hold"):
pads.hold.reset = 1
if hasattr(pads, "cs_n"):
self.comb += pads.cs_n.eq(spi.pads.cs_n)
self.comb += [
pads.mosi.eq(spi.pads.mosi),
spi.pads.miso.eq(pads.miso)
]
# Lattice ECP5 FPGAs SPI Flash (non-memory-mapped) ------------------------------------------------- # Lattice ECP5 FPGAs SPI Flash (non-memory-mapped) -------------------------------------------------