Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

boards/kc705: update sata integration.

This commit is contained in:
Florent Kermarrec 2020-11-02 19:01:10 +01:00
parent 5b4e4a3b4a
commit cc95d89a6f
1 changed files with 9 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

41
litex/boards/targets/kc705.py
View File

@ -89,20 +89,16 @@ class BaseSoC(SoCCore):
# SATA (Experimental) ---------------------------------------------------------------------- # SATA (Experimental) ----------------------------------------------------------------------
if with_sata: if with_sata:
from litex.build.generic_platform import Subsignal, Pins from litex.build.generic_platform import Subsignal, Pins
from litex.soc.interconnect import wishbone
from litesata.phy import LiteSATAPHY from litesata.phy import LiteSATAPHY
from litesata.core import LiteSATACore
from litesata.frontend.arbitration import LiteSATACrossbar
from litesata.frontend.dma import LiteSATABlock2MemDMA
# IOs # IOs
_sata_io = [ _sata_io = [
# SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter # SFP 2 SATA Adapter / https://shop.trenz-electronic.de/en/TE0424-01-SFP-2-SATA-Adapter
("sfp", 0, ("sfp2sata", 0,
Subsignal("txp", Pins("H2")), Subsignal("tx_p", Pins("H2")),
Subsignal("txn", Pins("H1")), Subsignal("tx_n", Pins("H1")),
Subsignal("rxp", Pins("G4")), Subsignal("rx_p", Pins("G4")),
Subsignal("rxn", Pins("G3")), Subsignal("rx_n", Pins("G3")),
), ),
] ]
platform.add_extension(_sata_io) platform.add_extension(_sata_io)
@ -116,33 +112,14 @@ class BaseSoC(SoCCore):
# PHY # PHY
self.submodules.sata_phy = LiteSATAPHY(platform.device, self.submodules.sata_phy = LiteSATAPHY(platform.device,
refclk = sata_refclk, refclk = sata_refclk,
pads = platform.request("sfp"), pads = platform.request("sfp2sata"),
gen = "gen1", gen = "gen2",
clk_freq = sys_clk_freq, clk_freq = sys_clk_freq,
data_width = 16) data_width = 16)
self.add_csr("sata_phy")
# Core # Core
self.submodules.sata_core = LiteSATACore(self.sata_phy) self.add_sata(phy=self.sata_phy, mode="read+write")
# Crossbar
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
# Block2Mem DMA
bus = wishbone.Interface(data_width=32, adr_width=32)
self.submodules.sata_block2mem = LiteSATABlock2MemDMA(
user_port = self.sata_crossbar.get_port(),
bus = bus,
endianness = self.cpu.endianness)
self.bus.add_master("sata_block2mem", master=bus)
self.add_csr("sata_block2mem")
# Timing constraints
platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/75e6)
platform.add_period_constraint(self.sata_phy.crg.cd_sata_tx.clk, 1e9/75e6)
self.platform.add_false_path_constraints(
self.crg.cd_sys.clk,
self.sata_phy.crg.cd_sata_tx.clk,
self.sata_phy.crg.cd_sata_tx.clk)
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser( self.submodules.leds = LedChaser(