soc/cores/spi: use new CSRField (no functional change)
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80b2bef387
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@ -10,11 +10,6 @@ from litex.soc.interconnect.csr import *
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# SPI Master ---------------------------------------------------------------------------------------
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SPI_CONTROL_START = 0
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SPI_CONTROL_LENGTH = 8
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SPI_STATUS_DONE = 0
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class SPIMaster(Module, AutoCSR):
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"""4-wire SPI Master
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@ -129,21 +124,24 @@ class SPIMaster(Module, AutoCSR):
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)
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def add_csr(self):
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self._control = CSRStorage(16)
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self._status = CSRStatus()
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self._control = CSRStorage(fields=[
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CSRField("start", size=1, offset=0, pulse=True),
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CSRField("length", size=8, offset=8)])
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self._status = CSRStatus(fields=[
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CSRField("done", size=1, offset=0)])
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self._mosi = CSRStorage(self.data_width)
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self._miso = CSRStatus(self.data_width)
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self._cs = CSRStorage(len(self.cs), reset=1)
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self._loopback = CSRStorage()
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self.comb += [
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self.start.eq(self._control.re & self._control.storage[SPI_CONTROL_START]),
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self.length.eq(self._control.storage[SPI_CONTROL_LENGTH:]),
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self.start.eq(self._control.fields.start),
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self.length.eq(self._control.fields.length),
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self.mosi.eq(self._mosi.storage),
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self.cs.eq(self._cs.storage),
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self.loopback.eq(self._loopback.storage),
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self._status.status[SPI_STATUS_DONE].eq(self.done),
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self._status.fields.done.eq(self.done),
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self._miso.status.eq(self.miso),
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]
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@ -360,7 +360,7 @@ class CSRStorage(_CompoundCSR):
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for field in [*fields]:
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field_assign = getattr(self.fields, field.name).eq(self.storage[field.offset:field.offset + field.size])
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if field.pulse:
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self.comb += If(self.storage.re, field_assign)
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self.comb += If(self.re, field_assign)
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else:
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self.comb += field_assign
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