framebuffer: chop memory words
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@ -2,7 +2,7 @@ from migen.fhdl.structure import *
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from migen.flow.actor import *
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from migen.flow.network import *
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from migen.flow import plumbing
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from migen.actorlib import ala, misc, dma_asmi
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from migen.actorlib import ala, misc, dma_asmi, structuring
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from migen.bank.description import *
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from migen.bank import csrgen
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@ -66,18 +66,30 @@ class _FrameInitiator(Actor):
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]
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return Fragment(comb)
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_bpp = 32
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_bpc = 10
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_pixel_layout = [
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("b", BV(_bpc)),
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("g", BV(_bpc)),
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("r", BV(_bpc)),
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("pad", BV(_bpp-3*_bpc))
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]
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class Framebuffer:
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def __init__(self, address, asmiport):
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asmi_bits = asmiport.hub.aw
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alignment_bits = asmiport.hub.dw//8
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length_bits = _hbits + _vbits + 2 - alignment_bits
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pack_factor = asmiport.hub.dw//_bpp
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packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor)
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fi = ActorNode(_FrameInitiator(asmi_bits, length_bits, alignment_bits))
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adrloop = ActorNode(misc.IntSequence(length_bits))
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adrbase = ActorNode(ala.Add(BV(asmi_bits)))
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adrbuffer = ActorNode(plumbing.Buffer)
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dma = ActorNode(dma_asmi.SequentialReader(asmiport))
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# TODO: chop
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cast = ActorNode(structuring.Cast(asmiport.hub.dw, packed_pixels))
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unpack = ActorNode(structuring.Unpack(pack_factor, _pixel_layout))
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# TODO: VTG
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g = DataFlowGraph()
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@ -86,6 +98,8 @@ class Framebuffer:
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g.add_connection(fi, adrbase, source_subr=["base"], sink_subr=["b"])
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g.add_connection(adrbase, adrbuffer)
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g.add_connection(adrbuffer, dma)
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g.add_connection(dma, cast)
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g.add_connection(cast, unpack)
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self._comp_actor = CompositeActor(g)
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self.bank = csrgen.Bank(fi.actor.get_registers(), address=address)
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