Merge pull request #1088 from enjoy-digital/ci-openrisc

CI: Add OpenRISC GCC toolchain installation.

.github/workflows/ci.yml

@@ -25,15 +25,18 @@ jobs:
       - name: Install LiteX
         run: |
           wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
-          python3 litex_setup.py init install --user
+          python3 litex_setup.py --init --install --user
 
-      # Install RISC-V GCC
+      # Install GCC Toolchains
-      - name: Install RISC-V GCC
+      - name: Install GCC Toolchains
         run: |
           wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
-          python3 litex_setup.py gcc
+          python3 litex_setup.py --gcc=riscv
           sudo mkdir /usr/local/riscv
           sudo cp -r $PWD/../riscv64-*/* /usr/local/riscv
+          python3 litex_setup.py --gcc=openrisc
+          sudo mkdir /usr/local/openrisc
+          sudo cp -r $PWD/../openrisc-*/* /usr/local/openrisc
 
       # Install Project
       - name: Install Project
@@ -43,4 +46,5 @@ jobs:
       - name: Run Tests
         run: |
           export PATH=/usr/local/riscv/bin:$PATH
+          export PATH=/usr/local/openrisc/bin:$PATH
           python3 setup.py test

litex/soc/cores/cpu/mor1kx/core.py

@@ -47,11 +47,6 @@ class MOR1KX(CPU):
             "csr"      : 0xe0000000,
         }
 
-    # GCC Triple.
-    @property
-    def gcc_triple(self):
-        return "or1k-elf"
-
     # GCC Flags.
     @property
     def gcc_flags(self):

test/test_cpu.py

@@ -10,7 +10,7 @@ import sys
 
 class TestCPU(unittest.TestCase):
     def boot_test(self, cpu_type):
-        cmd = f'lxsim --cpu-type={cpu_type}'
+        cmd = f'litex_sim --cpu-type={cpu_type}'
         litex_prompt = [b'\033\[[0-9;]+mlitex\033\[[0-9;]+m>']
         is_success = True
         with open("/tmp/test_boot_log", "wb") as result_file:
@@ -34,6 +34,7 @@ class TestCPU(unittest.TestCase):
 
         return is_success
 
+    # RISC-V CPUs.
     def test_vexriscv(self):
         self.assertTrue(self.boot_test("vexriscv"))
 
@@ -58,3 +59,6 @@ class TestCPU(unittest.TestCase):
     def test_minerva(self):
         self.assertTrue(self.boot_test("minerva"))
 
+    # OpenRISC CPUs.
+    #def test_mor1kx(self):
+    #    self.assertTrue(self.boot_test("mor1kx"))