integration/soc: add add_spi_flash method to add SPI Flash support to the SoC.
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@ -6,13 +6,14 @@
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import logging
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import logging
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import time
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import time
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import datetime
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import datetime
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from math import log2
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from math import log2, ceil
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from migen import *
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from migen import *
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from litex.soc.cores import cpu
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from litex.soc.cores import cpu
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from litex.soc.cores.identifier import Identifier
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from litex.soc.cores.identifier import Identifier
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from litex.soc.cores.timer import Timer
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from litex.soc.cores.timer import Timer
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from litex.soc.cores.spi_flash import SpiFlash
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from litex.soc.cores.spi import SPIMaster
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from litex.soc.cores.spi import SPIMaster
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect.csr import *
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@ -1045,8 +1046,7 @@ class LiteXSoC(SoC):
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dw = 32,
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dw = 32,
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interface = "wishbone",
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interface = "wishbone",
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endianness = self.cpu.endianness)
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endianness = self.cpu.endianness)
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ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None),
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ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=0x2000, cached=False)
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size=0x2000, cached=False)
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self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region)
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self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region)
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self.add_csr("ethmac")
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self.add_csr("ethmac")
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self.add_interrupt("ethmac")
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self.add_interrupt("ethmac")
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@ -1058,6 +1058,23 @@ class LiteXSoC(SoC):
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phy.crg.cd_eth_rx.clk,
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phy.crg.cd_eth_rx.clk,
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phy.crg.cd_eth_tx.clk)
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phy.crg.cd_eth_tx.clk)
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# Add SPI Flash --------------------------------------------------------------------------------
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def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None):
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assert dummy_cycles is not None # FIXME: Get dummy_cycles from SPI Flash
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assert mode in ["4x"] # FIXME: Add 1x support.
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if clk_freq is None: clk_freq = self.clk_freq/2 # FIXME: Get max clk_freq from SPI Flash
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spiflash = SpiFlash(
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pads = self.platform.request(name + mode),
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dummy = dummy_cycles,
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div = ceil(self.clk_freq/clk_freq),
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with_bitbang = True,
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endianness = self.cpu.endianness)
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spiflash.add_clk_primitive(self.platform.device)
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setattr(self.submodules, name, spiflash)
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self.add_memory_region(name, self.mem_map[name], 0x1000000) # FIXME: Get size from SPI Flash
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self.add_wb_slave(self.mem_map[name], spiflash.bus)
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self.add_csr(name)
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# Add SPI SDCard -------------------------------------------------------------------------------
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# Add SPI SDCard -------------------------------------------------------------------------------
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def add_spi_sdcard(self, name="spisdcard", clk_freq=400e3):
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def add_spi_sdcard(self, name="spisdcard", clk_freq=400e3):
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pads = self.platform.request(name)
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pads = self.platform.request(name)
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