soc/cores/clock/efinix: allows dyn_phase_shift configuration
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5d7e9c94a6
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cd439da18e
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@ -18,7 +18,7 @@ from litex.soc.cores.clock.common import *
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class EFINIXPLL(LiteXModule):
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n = 0
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nclkouts_max = 3
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def __init__(self, platform,version="V1_V2"):
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def __init__(self, platform,version="V1_V2", dyn_phase_shift_pads=[]):
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self.logger = logging.getLogger("EFINIXPLL")
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if version == "V1_V2":
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@ -45,6 +45,10 @@ class EFINIXPLL(LiteXModule):
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block["locked"] = self.name + "_locked"
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block["rstn"] = self.name + "_rstn"
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block["version"] = version
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if len(dyn_phase_shift_pads) > 0:
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block["shift_ena"] = dyn_phase_shift_pads["shift_ena"]
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block["shift"] = dyn_phase_shift_pads["shift"]
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block["shift_sel"] = dyn_phase_shift_pads["shift_sel"]
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self.platform.toolchain.ifacewriter.blocks.append(block)
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# Connect PLL's rstn/locked.
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@ -94,7 +98,7 @@ class EFINIXPLL(LiteXModule):
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self.logger.info("Use {}".format(colorer(block["resource"], "green")))
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def create_clkout(self, cd, freq, phase=0, margin=0, name="", with_reset=True):
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def create_clkout(self, cd, freq, phase=0, margin=0, name="", with_reset=True, dyn_phase=False):
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assert self.nclkouts < self.nclkouts_max
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clk_out_name = f"{self.name}_clkout{self.nclkouts}" if name == "" else name
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@ -114,7 +118,7 @@ class EFINIXPLL(LiteXModule):
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self.nclkouts += 1
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block = self.platform.toolchain.ifacewriter.get_block(self.name)
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block["clk_out"].append([clk_out_name, freq, phase, margin])
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block["clk_out"].append([clk_out_name, freq, phase, margin, dyn_phase])
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def extra(self, extra):
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block = self.platform.toolchain.ifacewriter.get_block(self.name)
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@ -133,8 +137,8 @@ class EFINIXPLL(LiteXModule):
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class TITANIUMPLL(EFINIXPLL):
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nclkouts_max = 5
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def __init__(self, platform):
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EFINIXPLL.__init__(self, platform, version="V3")
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def __init__(self, platform, dyn_phase_shift_pads=[]):
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EFINIXPLL.__init__(self, platform, version="V3", dyn_phase_shift_pads=dyn_phase_shift_pads)
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# Efinix / TRION ----------------------------------------------------------------------------------
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