soc: add l2 cache to spi_ram
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
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@ -2108,7 +2108,11 @@ class LiteXSoC(SoC):
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self.add_constant(f"{name}_DEBUG")
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self.add_constant(f"{name}_DEBUG")
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# Add SPI RAM --------------------------------------------------------------------------------
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# Add SPI RAM --------------------------------------------------------------------------------
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def add_spi_ram(self, name="spiram", mode="4x", clk_freq=20e6, module=None, phy=None, rate="1:1", software_debug=False, **kwargs):
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def add_spi_ram(self, name="spiram", mode="4x", clk_freq=20e6, module=None, phy=None, rate="1:1", software_debug=False,
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l2_cache_size = 8192,
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l2_cache_reverse = False,
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l2_cache_full_memory_we = True,
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**kwargs):
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# Imports.
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# Imports.
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from litespi import LiteSPI
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from litespi import LiteSPI
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from litespi.phy.generic import LiteSPIPHY
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from litespi.phy.generic import LiteSPIPHY
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@ -2132,8 +2136,28 @@ class LiteXSoC(SoC):
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spiram_core = LiteSPI(spiram_phy, mmap_endianness=self.cpu.endianness, with_mmap_write=True, **kwargs)
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spiram_core = LiteSPI(spiram_phy, mmap_endianness=self.cpu.endianness, with_mmap_write=True, **kwargs)
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self.add_module(name=f"{name}_core", module=spiram_core)
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self.add_module(name=f"{name}_core", module=spiram_core)
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spiram_region = SoCRegion(origin=self.mem_map.get(name, None), size=module.total_size)
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spiram_region = SoCRegion(origin=self.mem_map.get(name, None), size=module.total_size)
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self.bus.add_slave(name=name, slave=spiram_core.bus, region=spiram_region)
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# Create Wishbone Slave.
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wb_spiram = wishbone.Interface(data_width=32, address_width=32, addressing="word")
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self.bus.add_slave(name=name, slave=wb_spiram, region=spiram_region)
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self.comb += spiram_core.mmap.offset.eq(self.bus.regions.get(name, None).origin)
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self.comb += spiram_core.mmap.offset.eq(self.bus.regions.get(name, None).origin)
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# L2 Cache
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if l2_cache_size != 0:
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# Insert L2 cache inbetween Wishbone bus and LiteSPI
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l2_cache_size = max(l2_cache_size, int(2*32/8)) # Use minimal size if lower
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l2_cache_size = 2**int(log2(l2_cache_size)) # Round to nearest power of 2
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l2_cache = wishbone.Cache(
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cachesize = l2_cache_size//4,
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master = wb_spiram,
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slave = spiram_core.bus,
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reverse = l2_cache_reverse)
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if l2_cache_full_memory_we:
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l2_cache = FullMemoryWE()(l2_cache)
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self.l2_cache = l2_cache
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self.add_config("L2_SIZE", l2_cache_size)
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else:
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self.submodules += wishbone.Converter(wb_spiram, spiram_core.bus)
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# Constants.
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# Constants.
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self.add_constant(f"{name}_PHY_FREQUENCY", clk_freq)
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self.add_constant(f"{name}_PHY_FREQUENCY", clk_freq)
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