Update litex_json2dts_zephyr
Changes in Zephyr require updated script to generate correct overlay. This commit splits CSR regions that were being added to overlay as single register into separate registers with names. It also prints their size in bytes instead of used subregisters. I also added LITEX_CSR_DATA_WIDTH to generated config parameters. To limit code duplication, I added functions used for indenting text. Additionally, I updated formatting functions to take list of registers and then format it, instead of just surrounding already formatted text with braces.
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@ -22,49 +22,146 @@ import argparse
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import json
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def get_registers_of(name, csr):
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registers = csr['csr_registers']
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return [
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{
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**params,
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# describe size in bytes, not number of subregisters
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'size': params['size'] * 4,
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'name': r[len(name) + 1:],
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}
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for r, params in registers.items() if r.startswith(name)
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]
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# Indentation helpers
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INDENT_STR = ' '
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def indent(line, levels=1):
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return INDENT_STR * levels + line
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def indent_all(text, levels=1):
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return '\n'.join(map(indent, text.splitlines()))
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def indent_all_but_first(text, levels=1):
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lines = text.splitlines()
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indented = indent_all('\n'.join(lines[1:]), levels)
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if indented:
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return lines[0] + '\n' + indented
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else:
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return lines[0]
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# DTS formatting
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def dts_open(name, parm): return "&{} {{\n".format(parm.get('alias', name))
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def dts_close(): return "};\n"
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def dts_intr(name, csr): return " interrupts = <{} 0>;\n".format(
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hex(csr['constants'][name + '_interrupt']))
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def dts_reg(regs): return " reg = <{}>;\n".format(regs)
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def dts_open(name, parm):
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return "&{} {{\n".format(parm.get('alias', name))
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def dts_close():
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return "};\n"
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def dts_intr(name, csr):
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return indent("interrupts = <{} 0>;\n".format(
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hex(csr['constants'][name + '_interrupt'])
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))
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def dts_reg(regs):
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dtsi = 'reg = <'
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formatted_registers = '\n'.join(
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'0x{:x} 0x{:x}'.format(reg['addr'], reg['size'])
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for reg in regs
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)
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dtsi += indent_all_but_first(formatted_registers)
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dtsi += '>;'
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return indent_all(dtsi) + '\n'
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def dts_reg_names(regs):
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dtsi = 'reg-names = '
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formatted_registers = ',\n'.join(
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'"{}"'.format(reg['name'])
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for reg in regs
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)
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dtsi += indent_all_but_first(formatted_registers)
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dtsi += ';'
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return indent_all(dtsi) + '\n'
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# DTS handlers
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def disabled_handler(name, parm, csr):
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return " status = \"disabled\";\n"
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return indent('status = "disabled";\n')
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def ram_handler(name, parm, csr):
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return dts_reg(" ".join([
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hex(csr['memories'][name]['base']),
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hex(csr['memories'][name]['size'])]))
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mem_reg = {
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'addr': csr['memories'][name]['base'],
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'size': csr['memories'][name]['size'],
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}
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return dts_reg([mem_reg])
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def ethmac_handler(name, parm, csr):
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dtsi = dts_reg(" ".join([
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hex(csr['csr_bases'][name]),
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hex(parm['size']),
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hex(csr['memories'][name]['base']),
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hex(csr['memories'][name]['size'])]))
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rx_registers = get_registers_of(name + '_sram_writer', csr)
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for reg in rx_registers:
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reg['name'] = 'rx_' + reg['name']
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tx_registers = get_registers_of(name + '_sram_reader', csr)
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for reg in tx_registers:
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reg['name'] = 'tx_' + reg['name']
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eth_buffers = {
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'name': 'buffers',
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'addr': csr['memories'][name]['base'],
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'size': csr['memories'][name]['size'],
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'type': csr['memories'][name]['type'],
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}
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registers = rx_registers + tx_registers + [eth_buffers]
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dtsi = dts_reg(registers)
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dtsi += dts_reg_names(registers)
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dtsi += dts_intr(name, csr)
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return dtsi
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def i2c_handler(name, parm, csr):
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dtsi = dts_reg(" ".join([
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hex(csr['csr_bases'][name]),
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hex(parm['size']),
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hex(csr['csr_bases'][name] + parm['size']),
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hex(parm['size'])]))
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dtsi += dts_intr(name, csr)
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registers = get_registers_of(name, csr)
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if len(registers) == 0:
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raise KeyError
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for reg in registers:
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if reg["name"] == "w":
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reg["name"] = "write"
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elif reg["name"] == "r":
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reg["name"] = "read"
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dtsi = dts_reg(registers)
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dtsi += dts_reg_names(registers)
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return dtsi
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def peripheral_handler(name, parm, csr):
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dtsi = dts_reg(" ".join([
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hex(csr['csr_bases'][name]),
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hex(parm['size'])]))
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registers = get_registers_of(name, csr)
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if len(registers) == 0:
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raise KeyError
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dtsi = dts_reg(registers)
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dtsi += dts_reg_names(registers)
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try:
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dtsi += dts_intr(name, csr)
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except KeyError as e:
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@ -76,29 +173,24 @@ overlay_handlers = {
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'uart': {
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'handler': peripheral_handler,
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'alias': 'uart0',
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'size': 0x20,
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'config_entry': 'UART_LITEUART'
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},
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'timer0': {
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'handler': peripheral_handler,
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'size': 0x40,
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'config_entry': 'LITEX_TIMER'
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},
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'ethmac': {
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'handler': ethmac_handler,
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'alias': 'eth0',
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'size': 0x80,
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'config_entry': 'ETH_LITEETH'
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},
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'spiflash': {
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'handler': peripheral_handler,
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'alias': 'spi0',
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'size': 12,
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'config_entry': 'SPI_LITESPI'
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},
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'i2c0' : {
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'handler': i2c_handler,
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'size': 0x4,
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'config_entry': 'I2C_LITEX'
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},
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'main_ram': {
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@ -108,7 +200,6 @@ overlay_handlers = {
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'identifier_mem': {
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'handler': peripheral_handler,
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'alias': 'dna0',
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'size': 0x100,
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}
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}
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@ -137,6 +228,10 @@ def generate_dts_config(csr):
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if name not in overlay_handlers.keys():
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print('No overlay handler for:', name, 'at', hex(value))
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cnf += ' -DCONFIG_LITEX_CSR_DATA_WIDTH={}'.format(
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csr['constants']['config_csr_data_width'],
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)
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return dts, cnf
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