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README: update RISC-V toolchain

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Florent Kermarrec 2019-05-25 09:24:25 +02:00
parent 7e837bf1d0
commit cd543b290c
1 changed files with 3 additions and 3 deletions
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@ -99,9 +99,9 @@ FPGA lessons/tutorials can be found at: https://github.com/enjoy-digital/fpga_10
./litex_setup.py update
2. Install a RISC-V toolchain:
wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz
tar -xvf riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz
export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin/
wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
tar -xvf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
3. Build the target of your board...:
Go to boards/targets and execute the target you want to build