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soc/sdram: add workaround for Vivado issue with our L2 cache, reported to Xilinx in november 2014, remove it when fixed by Xilinx

This commit is contained in:
Florent Kermarrec 2015-03-12 17:12:35 +01:00
parent 767d45727a
commit cd6c04b24f
1 changed files with 9 additions and 1 deletions
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10
misoclib/soc/sdram.py
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@ -50,7 +50,15 @@ class SDRAMSoC(SoC):
self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
if self.with_l2:
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())
# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
# Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
# Remove this workaround when fixed by Xilinx.
from mibuild.xilinx.vivado import XilinxVivadoPlatform
if isinstance(self.platform, XilinxVivadoPlatform):
from migen.fhdl.simplify import FullMemoryWE
self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master()))
else:
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())
lasmic = self.sdram.controller.lasmic
sdram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8
self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, sdram_size)