soc/interconnect/packet/Dispatcher: Add missing **kwargs.
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@ -94,7 +94,7 @@ class Dispatcher(LiteXModule):
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idx = 2**i
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idx = 2**i
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else:
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else:
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idx = i
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idx = i
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cases[idx] = [master.connect(slave)]
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cases[idx] = [master.connect(slave, **kwargs)]
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cases["default"] = [master.ready.eq(1)]
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cases["default"] = [master.ready.eq(1)]
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self.comb += Case(sel, cases)
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self.comb += Case(sel, cases)
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