Merge pull request #1651 from trabucayre/gowinpll_complete_support
soc/cores/clock/gowin_gw1n: add support for CLKOUTP, CLKOUTD, CLKOUTD3, phase and divisor
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enjoy-digital
GitHub
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cd933da3ac
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@ -48,7 +48,7 @@ class GW1NOSC(Module):
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# GoWin / GW1NPLL ----------------------------------------------------------------------------------
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class GW1NPLL(Module):
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nclkouts_max = 1
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nclkouts_max = 4
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def __init__(self, devicename, device, vco_margin=0):
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self.logger = logging.getLogger("GW1NPLL")
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@ -120,6 +120,9 @@ class GW1NPLL(Module):
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self.nclkouts += 1
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def compute_config(self):
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# extract the highest frequency and associated margin
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freq_max, m = max([(f, n) for (_, f, _, n) in self.clkouts.values()], key=lambda p: p[1])
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configs = [] # corresponding VCO/FBDIV/IDIV/ODIV params + diff
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for idiv in range(1, 64):
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@ -134,28 +137,82 @@ class GW1NPLL(Module):
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(vco_freq_min, vco_freq_max) = self.vco_freq_range
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if (vco_freq >= vco_freq_min*(1 + self.vco_margin) and
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vco_freq <= vco_freq_max*(1 - self.vco_margin)):
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for _n, (clk, f, p, _m) in sorted(self.clkouts.items()):
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diff = abs(out_freq - f)
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if diff <= f*_m:
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configs.append({
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"diff" : diff,
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"idiv" : idiv,
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"odiv" : odiv,
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"vco" : vco_freq,
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"fdiv" : fdiv
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})
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diff = abs(out_freq - freq_max)
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if diff <= freq_max*m:
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configs.append({
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"diff" : diff,
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"idiv" : idiv,
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"odiv" : odiv,
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"vco" : vco_freq,
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"fdiv" : fdiv
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})
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if len(configs) == 0:
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raise ValueError("No PLL config found")
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return configs[min([(i, v["diff"]) for i, v in enumerate(configs)], key=lambda p: p[1])[0]]
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# select better combo (where diff f_real-f_req is the smallest)
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config = configs[min([(i, v["diff"]) for i, v in enumerate(configs)], key=lambda p: p[1])[0]]
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# out_freq using the selected configuration
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out_freq = self.clkin_freq*config["fdiv"] / config["idiv"]
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# Phase
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phases = list({p for (_, _, p, _) in self.clkouts.values() if p != 0})
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assert len(phases) < 2 # only zero or one phase possible
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# configure phase param
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config["PSDA_SEL"] = f"{int(phases[0] // 22.5):04b}" if len(phases) == 1 else "0000"
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# frequencies
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# CLKOUT & CLKOUTP : VCODIV / 1
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# CLKOUTD3 : VCODIV / 3
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# CLKOUTD : VCODIV / an even value [2-128]
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# FIXME: bypass may used to directly connect output clock to the input
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freqs_div = [freq_max // f for (_, f, _, _) in self.clkouts.values() if freq_max // f != 1]
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if len(freqs_div) > 2:
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raise ValueError("Gowin PLL can't have more than two divisor")
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clkoutd_div = [d for d in freqs_div if d != 3] # extracts divisor by an even value
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if (len(freqs_div) == 2 and freqs_div.count(3) == 2) or (len(clkoutd_div) == 2) or \
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(len(clkoutd_div) == 1 and clkoutd_div[0] % 2 != 0):
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raise ValueError("Gowin PLL has two divisor: one /3 and an even divisor between 2 and 128")
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# configure sdiv for CLKOUTD (if it's required)
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config["SDIV_SEL"] = int(clkoutd_div[0]) if len(clkoutd_div) == 1 else 2
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for c, (clock, freq, phase, margin) in self.clkouts.items():
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th_div = int(freq_max // freq) # divisor to apply
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r_freq = out_freq / th_div # real frequency
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diff_f = abs(r_freq - freq) # diff between obtained and requested
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# check if value fit criterion
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if diff_f > r_freq*margin:
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raise ValueError(f"Can't obtain requested frequency {diff_f} > {r_freq * margin}")
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if th_div == 1: # no divisor: may be CLKOUT or CLKOUTP
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if phase == 0:
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out = "" # CLKOUT
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else:
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if "CLKOUTP" in config.keys():
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raise ValueError("Only one clock with freq == freq max and a phase != 0")
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out = "P"
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elif th_div == 3:
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out = "D3"
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else:
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out = "D"
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config.update({
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f"CLKOUT{out}" : clock,
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f"CLKOUT{out}_SRC" : "CLKOUT" if phase == 0 else "CLKOUTP",
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})
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return config
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def do_finalize(self):
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assert hasattr(self, "clkin")
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assert len(self.clkouts) == 1
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assert len(self.clkouts) > 0 and len(self.clkouts) <= 4
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config = self.compute_config()
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# Based on UG286-1.3E Note.
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self.params.update(
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# Parameters.
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p_DEVICE = self.devicename, # FPGA Device.
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p_DEVICE = self.devicename, # FPGA Device.
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p_FCLKIN = str(self.clkin_freq/1e6), # Clk Input frequency (MHz).
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p_DYN_IDIV_SEL = "false", # Disable dynamic IDIV.
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p_IDIV_SEL = config["idiv"]-1, # Static IDIV value (1-64).
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@ -163,7 +220,7 @@ class GW1NPLL(Module):
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p_FBDIV_SEL = config["fdiv"]-1, # Static FBDIV value (1-64).
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p_DYN_ODIV_SEL = "false", # Disable dynamic ODIV.
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p_ODIV_SEL = config["odiv"], # Static ODIV value.
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p_PSDA_SEL = "0000", # -
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p_PSDA_SEL = config["PSDA_SEL"], # -
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p_DYN_DA_EN = "false", # -
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p_DUTYDA_SEL = "1000", # -
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p_CLKOUT_FT_DIR = 1, # -
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@ -174,9 +231,7 @@ class GW1NPLL(Module):
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p_CLKOUT_BYPASS = "false", # Clk Input to CLKOUT bypass.
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p_CLKOUTP_BYPASS = "false", # Clk Input to CLKOUTP bypass.
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p_CLKOUTD_BYPASS = "false", # Clk Input to CLKOUTD bypass.
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p_DYN_SDIV_SEL = 2, # Disable dynamic SDIV.
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p_CLKOUTD_SRC = "CLKOUT", # Recopy CLKOUT to CLKOUTD.
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p_CLKOUTD3_SRC = "CLKOUT", # Recopy CLKOUT to CLKOUTD3.
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p_DYN_SDIV_SEL = config["SDIV_SEL"], # Disable dynamic SDIV.
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# Inputs.
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i_CLKIN = self.clkin, # Clk Input.
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@ -205,13 +260,10 @@ class GW1NPLL(Module):
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i_RESET_I = 0, # IDIV reset.
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i_RESET_S = 0, # SDIV and DIV3 reset.
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)
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clk0, f0, p0, m0 = self.clkouts[0]
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self.params.update(
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# Outputs.
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o_LOCK = self.locked, # PLL lock status.
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o_CLKOUT = clk0, # Clock output.
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o_CLKOUTP = Open(), # Clock output (With phase and duty cycle adjustement).
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o_CLKOUTD = Open(), # Clock divided from CLKOUT and CLKOUTP (controlled by SDIV).
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o_CLKOUTD3 = Open(), # Clock divided from CLKOUT and CLKOUTP (constant division of 3).
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)
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for clk_name in ["CLKOUT", "CLKOUTP", "CLKOUTD", "CLKOUTD3"]:
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self.params[f"o_{clk_name}"] = config.get(clk_name, Open()) # Clock output.
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if clk_name in ["CLKOUTD", "CLKOUTD3"]: # Recopy CLKOUTx to CLKOUTDx
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self.params[f"p_{clk_name}_SRC"] = config.get(f"{clk_name}_SRC", "CLKOUT")
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self.params.update(o_LOCK=self.locked) # PLL lock status.
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self.specials += Instance(instance_name, **self.params)
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