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integration/soc/add_etherbone: expose buffer_depth.

This commit is contained in:
Florent Kermarrec 2020-11-23 17:50:31 +01:00
parent a1bfa79092
commit cddf19df98
1 changed files with 6 additions and 4 deletions
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10
litex/soc/integration/soc.py
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@ -1335,9 +1335,10 @@ class LiteXSoC(SoC):
# Add Etherbone -------------------------------------------------------------------------------- # Add Etherbone --------------------------------------------------------------------------------
def add_etherbone(self, name="etherbone", phy=None, def add_etherbone(self, name="etherbone", phy=None,
mac_address = 0x10e2d5000000, mac_address = 0x10e2d5000000,
ip_address = "192.168.1.50", ip_address = "192.168.1.50",
udp_port = 1234): udp_port = 1234,
buffer_depth = 4):
# Imports # Imports
from liteeth.core import LiteEthUDPIPCore from liteeth.core import LiteEthUDPIPCore
from liteeth.frontend.etherbone import LiteEthEtherbone from liteeth.frontend.etherbone import LiteEthEtherbone
@ -1356,9 +1357,10 @@ class LiteXSoC(SoC):
self.comb += self.cd_etherbone.rst.eq(ResetSignal("sys")) self.comb += self.cd_etherbone.rst.eq(ResetSignal("sys"))
# Etherbone # Etherbone
etherbone = LiteEthEtherbone(ethcore.udp, udp_port, cd="etherbone") etherbone = LiteEthEtherbone(ethcore.udp, udp_port, buffer_depth=buffer_depth, cd="etherbone")
setattr(self.submodules, name, etherbone) setattr(self.submodules, name, etherbone)
self.add_wb_master(etherbone.wishbone.bus) self.add_wb_master(etherbone.wishbone.bus)
# Timing constraints # Timing constraints
if hasattr(phy, "crg"): if hasattr(phy, "crg"):
eth_rx_clk = phy.crg.cd_eth_rx.clk eth_rx_clk = phy.crg.cd_eth_rx.clk