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fhdl/verilog: Simplify _print_signal/_print_constant, add comments to _print_expression.

This commit is contained in:
Florent Kermarrec 2021-10-15 11:51:39 +02:00
parent a18107f795
commit cdfb8d141a
1 changed files with 24 additions and 16 deletions
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40
litex/gen/fhdl/verilog.py
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@ -85,31 +85,33 @@ _ieee_1800_2017_verilog_reserved_keywords = {
# Print Signal ------------------------------------------------------------------------------------- # Print Signal -------------------------------------------------------------------------------------
def _print_signal(ns, s): def _print_signal(ns, s):
if s.signed: return "{signed}{vector}{name}".format(
n = "signed " signed = "" if (not s.signed) else "signed ",
else: vector = "" if ( len(s) <= 1) else f"[{str(len(s)-1) }:0] ",
n = "" name = ns.get_name(s)
if len(s) > 1: )
n += "[" + str(len(s)-1) + ":0] "
n += ns.get_name(s)
return n
# Print Constant ----------------------------------------------------------------------------------- # Print Constant -----------------------------------------------------------------------------------
def _print_constant(node): def _print_constant(node):
if node.signed: return "{sign}{bits}'d{value}".format(
sign = "-" if node.value < 0 else "" sign = "" if node.value >= 0 else "-",
return (sign + str(node.nbits) + "'d" + str(abs(node.value)), True) bits = str(node.nbits),
else: value = abs(node.value),
return str(node.nbits) + "'d" + str(node.value), False ), node.signed
# Print Expression --------------------------------------------------------------------------------- # Print Expression ---------------------------------------------------------------------------------
def _print_expression(ns, node): def _print_expression(ns, node):
# Constant.
if isinstance(node, Constant): if isinstance(node, Constant):
return _print_constant(node) return _print_constant(node)
# Signal.
elif isinstance(node, Signal): elif isinstance(node, Signal):
return ns.get_name(node), node.signed return ns.get_name(node), node.signed
# Operator.
elif isinstance(node, _Operator): elif isinstance(node, _Operator):
arity = len(node.operands) arity = len(node.operands)
r1, s1 = _print_expression(ns, node.operands[0]) r1, s1 = _print_expression(ns, node.operands[0])
@ -145,11 +147,13 @@ def _print_expression(ns, node):
else: else:
raise TypeError raise TypeError
return "(" + r + ")", s return "(" + r + ")", s
# Slice.
elif isinstance(node, _Slice): elif isinstance(node, _Slice):
# Verilog does not like us slicing non-array signals... # Verilog does not like us slicing non-array signals...
if isinstance(node.value, Signal) \ if (isinstance(node.value, Signal) and
and len(node.value) == 1 \ len(node.value) == 1 and
and node.start == 0 and node.stop == 1: node.start == 0 and node.stop == 1):
return _print_expression(ns, node.value) return _print_expression(ns, node.value)
if node.start + 1 == node.stop: if node.start + 1 == node.stop:
@ -158,9 +162,13 @@ def _print_expression(ns, node):
sr = "[" + str(node.stop-1) + ":" + str(node.start) + "]" sr = "[" + str(node.stop-1) + ":" + str(node.start) + "]"
r, s = _print_expression(ns, node.value) r, s = _print_expression(ns, node.value)
return r + sr, s return r + sr, s
# Cat.
elif isinstance(node, Cat): elif isinstance(node, Cat):
l = [_print_expression(ns, v)[0] for v in reversed(node.l)] l = [_print_expression(ns, v)[0] for v in reversed(node.l)]
return "{" + ", ".join(l) + "}", False return "{" + ", ".join(l) + "}", False
# Replicate.
elif isinstance(node, Replicate): elif isinstance(node, Replicate):
return "{" + str(node.n) + "{" + _print_expression(ns, node.v)[0] + "}}", False return "{" + str(node.n) + "{" + _print_expression(ns, node.v)[0] + "}}", False
else: else: