build/microsemi/libero_soc: small cleanup
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@ -48,6 +48,7 @@ def _build_io_pdc(named_sc, named_pc, build_name, additional_io_constraints):
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pdc += "\n".join(additional_io_constraints)
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tools.write_to_file(build_name + "_io.pdc", pdc)
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def _build_fp_pdc(build_name, additional_fp_constraints):
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pdc = "\n".join(additional_fp_constraints)
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tools.write_to_file(build_name + "_fp.pdc", pdc)
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@ -225,31 +226,33 @@ class MicrosemiLiberoSoCPolarfireToolchain:
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def build(self, platform, fragment, build_dir="build", build_name="top",
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toolchain_path=None, run=False, **kwargs):
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# create build directory
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os.makedirs(build_dir, exist_ok=True)
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cwd = os.getcwd()
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os.chdir(build_dir)
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# finalized design
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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# generate verilog
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# generate top module
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top_output = platform.get_verilog(fragment, name=build_name, **kwargs)
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named_sc, named_pc = platform.resolve_signals(top_output.ns)
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top_file = build_name + ".v"
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top_output.write(top_file)
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platform.add_source(top_file)
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# generate design script (tcl)
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# generate design script file (.tcl)
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_build_tcl(platform, platform.sources, build_dir, build_name)
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# generate design io constraints (pdc)
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# generate design io constraints file (.pdc)
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_build_io_pdc(named_sc, named_pc, build_name, self.additional_io_constraints)
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# generate design fp constraints (pdc)
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# generate design fp constraints file (.pdc)
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_build_fp_pdc(build_name, self.additional_fp_constraints)
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# generate design timing constraints (sdc)
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# generate design timing constraints file (sdc)
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_build_timing_sdc(top_output.ns, self.clocks, self.false_paths, build_name,
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self.additional_timing_constraints)
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