integration/soc: Fix typo.

2021-11-14 09:43:00 +01:00 · 2021-11-14 09:43:00 +01:00 · ce96668ebd
parent 8d7196d567
commit ce96668ebd
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -925,7 +925,7 @@ class SoC(Module):

        # Add Bus Masters/CSR/IRQs.
        if not isinstance(self.cpu, (cpu.CPUNone, cpu.Zynq7000)):
-            if hasattr(cpu, "set_reset_address"):
+            if hasattr(self.cpu, "set_reset_address"):
                if reset_address is None:
                    reset_address = self.mem_map["rom"]
                self.cpu.set_reset_address(reset_address)