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cf1c5d99b3
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@ -268,23 +268,24 @@ class XilinxVivadoToolchain:
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# The asynchronous input to a MultiReg is a false path
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# The asynchronous input to a MultiReg is a false path
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platform.add_platform_command(
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platform.add_platform_command(
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"set_false_path -quiet "
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"set_false_path -quiet "
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"-to [get_nets -quiet -filter {{mr_ff == TRUE}}]"
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"-through [get_nets -hierarchical -filter {{mr_ff == TRUE}}]"
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)
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)
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# The asychronous reset input to the AsyncResetSynchronizer is a false path
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# The asychronous reset input to the AsyncResetSynchronizer is a false path
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platform.add_platform_command(
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platform.add_platform_command(
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"set_false_path -quiet "
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"set_false_path -quiet "
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"-to [get_pins -quiet -filter {{REF_PIN_NAME == PRE}} "
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"-to [get_pins -filter {{REF_PIN_NAME == PRE}} "
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"-of [get_cells -quiet -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]"
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"-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]"
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)
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)
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# clock_period-2ns to resolve metastability on the wire between the AsyncResetSynchronizer FFs
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# clock_period-2ns to resolve metastability on the wire between the AsyncResetSynchronizer FFs
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platform.add_platform_command(
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platform.add_platform_command(
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"set_max_delay 2 -quiet "
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"set_max_delay 2 -quiet "
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"-from [get_pins -quiet -filter {{REF_PIN_NAME == Q}} "
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"-from [get_pins -filter {{REF_PIN_NAME == C}} "
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"-of [get_cells -quiet -filter {{ars_ff1 == TRUE}}]] "
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"-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE}}]] "
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"-to [get_pins -quiet -filter {{REF_PIN_NAME == D}} "
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"-to [get_pins -filter {{REF_PIN_NAME == D}} "
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"-of [get_cells -quiet -filter {{ars_ff2 == TRUE}}]]"
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"-of_objects [get_cells -hierarchical -filter {{ars_ff2 == TRUE}}]]"
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)
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)
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def build(self, platform, fragment,
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def build(self, platform, fragment,
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build_dir = "build",
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build_dir = "build",
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build_name = "top",
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build_name = "top",
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