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Merge pull request #448 from kessam/patch-1 

Fix timing constraints
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enjoy-digital 2020-04-06 11:12:12 +02:00 committed by GitHub
parent 6043108376 fb532f5e92
commit cf1c5d99b3
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1 changed files with 9 additions and 8 deletions
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15
litex/build/xilinx/vivado.py
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@ -268,23 +268,24 @@ class XilinxVivadoToolchain:
# The asynchronous input to a MultiReg is a false path
platform.add_platform_command(
"set_false_path -quiet "
"-to [get_nets -quiet -filter {{mr_ff == TRUE}}]"
"-through [get_nets -hierarchical -filter {{mr_ff == TRUE}}]"
)
# The asychronous reset input to the AsyncResetSynchronizer is a false path
platform.add_platform_command(
"set_false_path -quiet "
"-to [get_pins -quiet -filter {{REF_PIN_NAME == PRE}} "
"-of [get_cells -quiet -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]"
"-to [get_pins -filter {{REF_PIN_NAME == PRE}} "
"-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE || ars_ff2 == TRUE}}]]"
)
# clock_period-2ns to resolve metastability on the wire between the AsyncResetSynchronizer FFs
platform.add_platform_command(
"set_max_delay 2 -quiet "
"-from [get_pins -quiet -filter {{REF_PIN_NAME == Q}} "
"-of [get_cells -quiet -filter {{ars_ff1 == TRUE}}]] "
"-to [get_pins -quiet -filter {{REF_PIN_NAME == D}} "
"-of [get_cells -quiet -filter {{ars_ff2 == TRUE}}]]"
"-from [get_pins -filter {{REF_PIN_NAME == C}} "
"-of_objects [get_cells -hierarchical -filter {{ars_ff1 == TRUE}}]] "
"-to [get_pins -filter {{REF_PIN_NAME == D}} "
"-of_objects [get_cells -hierarchical -filter {{ars_ff2 == TRUE}}]]"
)
def build(self, platform, fragment,
build_dir = "build",
build_name = "top",