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soc/interconnect/stream_sim: adapt to new simulator

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This commit is contained in:
Florent Kermarrec 2016-03-21 19:56:43 +01:00
parent 703b30e078
commit cf29ee0b91
1 changed files with 49 additions and 43 deletions
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92
litex/soc/interconnect/stream_sim.py
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@ -115,28 +115,30 @@ class PacketStreamer(Module):
while not packet.done: while not packet.done:
yield yield
def do_simulation(self, selfp): def generator(self):
if len(self.packets) and self.packet.done: while True:
self.packet = self.packets.pop(0) if len(self.packets) and self.packet.done:
if not self.packet.ongoing and not self.packet.done: self.packet = self.packets.pop(0)
selfp.source.valid = 1 if not self.packet.ongoing and not self.packet.done:
selfp.source.data = self.packet.pop(0) yield self.source.valid.eq(1)
self.packet.ongoing = True yield self.source.data.eq(self.packet.pop(0))
elif selfp.source.valid == 1 and selfp.source.ready == 1: self.packet.ongoing = True
if len(self.packet) == 1: elif (yield self.source.valid) == 1 and (yield self.source.ready) == 1:
selfp.source.last = 1 if len(self.packet) == 1:
if self.last_be is not None: yield self.source.last.eq(1)
selfp.source.last_be = self.last_be if self.last_be is not None:
else: yield self.source.last_be.eq(self.last_be)
selfp.source.last = 0 else:
if self.last_be is not None: yield self.source.last.eq(0)
selfp.source.last_be = 0 if self.last_be is not None:
if len(self.packet) > 0: yield self.source.last_be.eq(0)
selfp.source.valid = 1 if len(self.packet) > 0:
selfp.source.data = self.packet.pop(0) yield self.source.valid.eq(1)
else: yield self.source.data.eq(self.packet.pop(0))
self.packet.done = True else:
selfp.source.valid = 0 self.packet.done = True
yield self.source.valid.eq(0)
yield
class PacketLogger(Module): class PacketLogger(Module):
@ -153,18 +155,20 @@ class PacketLogger(Module):
while not self.packet.done: while not self.packet.done:
yield yield
def do_simulation(self, selfp): def generator(self):
selfp.sink.ready = 1 while True:
if selfp.sink.valid: yield self.sink.ready.eq(1)
if self.first: if (yield self.sink.valid):
self.packet = Packet() if self.first:
self.packet.append(selfp.sink.data) self.packet = Packet()
self.first = False self.packet.append((yield self.sink.data))
else: self.first = False
self.packet.append(selfp.sink.data) else:
if selfp.sink.last: self.packet.append((yield self.sink.data))
self.packet.done = True if (yield self.sink.last):
self.first = True self.packet.done = True
self.first = True
yield
class AckRandomizer(Module): class AckRandomizer(Module):
@ -174,21 +178,23 @@ class AckRandomizer(Module):
self.sink = stream.Endpoint(description) self.sink = stream.Endpoint(description)
self.source = stream.Endpoint(description) self.source = stream.Endpoint(description)
self.run = Signal() self.ce = Signal(reset=1)
self.comb += \ self.comb += \
If(self.run, If(self.ce,
self.sink.connect(self.source) Record.connect(self.sink, self.source)
).Else( ).Else(
self.source.valid.eq(0), self.source.valid.eq(0),
self.sink.ready.eq(0), self.sink.ready.eq(0),
) )
def do_simulation(self, selfp): def generator(self):
n = randn(100) while True:
if n < self.level: n = randn(100)
selfp.run = 0 if n < self.level:
else: yield self.ce.eq(0)
selfp.run = 1 else:
yield self.ce.eq(1)
yield
# XXX # XXX