Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

boards/targets: revert default sys_clk_freq on nexys4ddr/versa_ecp5 (but add parameter to configure it)

Browse source
This commit is contained in:
Florent Kermarrec 2019-05-24 09:37:33 +02:00
parent aa640f2999
commit cf369c437c
2 changed files with 8 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
litex/boards/targets/nexys4ddr.py
View file

@ -47,7 +47,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM): class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(50e6), **kwargs): def __init__(self, sys_clk_freq=int(100e6), **kwargs):
platform = nexys4ddr.Platform() platform = nexys4ddr.Platform()
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000, integrated_rom_size=0x8000,
@ -102,12 +102,14 @@ def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR") parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR")
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
parser.add_argument("--sys-clk-freq", default=75e6,
help="system clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet", action="store_true", parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support") help="enable Ethernet support")
args = parser.parse_args() args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args)) soc = cls(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build() builder.build()

6
litex/boards/targets/versa_ecp5.py
View file

@ -73,7 +73,7 @@ class _CRG(Module):
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCSDRAM): class BaseSoC(SoCSDRAM):
def __init__(self, sys_clk_freq=int(50e6), toolchain="diamond", **kwargs): def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
platform = versa_ecp5.Platform(toolchain=toolchain) platform = versa_ecp5.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
integrated_rom_size=0x8000, integrated_rom_size=0x8000,
@ -130,12 +130,14 @@ def main():
help='gateware toolchain to use, diamond (default) or trellis') help='gateware toolchain to use, diamond (default) or trellis')
builder_args(parser) builder_args(parser)
soc_sdram_args(parser) soc_sdram_args(parser)
parser.add_argument("--sys-clk-freq", default=75e6,
help="system clock frequency (default=75MHz)")
parser.add_argument("--with-ethernet", action="store_true", parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support") help="enable Ethernet support")
args = parser.parse_args() args = parser.parse_args()
cls = EthernetSoC if args.with_ethernet else BaseSoC cls = EthernetSoC if args.with_ethernet else BaseSoC
soc = cls(toolchain=args.toolchain, **soc_sdram_argdict(args)) soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args)) builder = Builder(soc, **builder_argdict(args))
builder.build() builder.build()