Write init files that respect CPU's endianness.
This is required for PicoRV32 support. We also drive-by enable explicit specification of run= in Builder.build() by callers.
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7176492231
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cf74c781f4
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@ -130,13 +130,17 @@ class Builder:
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def _initialize_rom(self):
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def _initialize_rom(self):
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bios_file = os.path.join(self.output_dir, "software", "bios",
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bios_file = os.path.join(self.output_dir, "software", "bios",
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"bios.bin")
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"bios.bin")
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endianness = cpu_interface.cpu_endianness[self.soc.cpu_type]
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with open(bios_file, "rb") as boot_file:
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with open(bios_file, "rb") as boot_file:
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boot_data = []
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boot_data = []
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while True:
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while True:
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w = boot_file.read(4)
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w = boot_file.read(4)
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if not w:
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if not w:
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break
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break
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boot_data.append(struct.unpack(">I", w)[0])
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if endianness == 'little':
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boot_data.append(struct.unpack("<I", w)[0])
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else:
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boot_data.append(struct.unpack(">I", w)[0])
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self.soc.initialize_rom(boot_data)
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self.soc.initialize_rom(boot_data)
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def build(self, toolchain_path=None, **kwargs):
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def build(self, toolchain_path=None, **kwargs):
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@ -157,9 +161,11 @@ class Builder:
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if self.gateware_toolchain_path is not None:
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if self.gateware_toolchain_path is not None:
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toolchain_path = self.gateware_toolchain_path
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toolchain_path = self.gateware_toolchain_path
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if 'run' not in kwargs:
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kwargs['run'] = self.compile_gateware
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vns = self.soc.build(build_dir=os.path.join(self.output_dir, "gateware"),
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vns = self.soc.build(build_dir=os.path.join(self.output_dir, "gateware"),
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run=self.compile_gateware, toolchain_path=toolchain_path,
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toolchain_path=toolchain_path, **kwargs)
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**kwargs)
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return vns
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return vns
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